Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1999-01-29
2001-12-04
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S975000, C438S976000
Reexamination Certificate
active
06326278
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device which uses an alignment mark in order to cause an overlapping of a lower layer pattern and an upper layer pattern and, more particularly, to a method for manufacturing a semiconductor device which can prevent an alignment mark from being changed in shape.
2. Description of the Related Art
In a lithography step of a manufacturing process for a semiconductor device, in order to cause an overlapping with a high precision of a lower layer pattern and an upper layer pattern, there has hitherto been executed a method wherein an alignment mark is formed on the lower layer pattern and, using this alignment mark as a basis, a mask for use on the upper layer pattern is positionally aligned.
FIGS. 1A
to
1
G are sectional views illustrating in the sequential step order a conventional method for manufacturing a semiconductor device.
In the conventional method for manufacturing a semiconductor device, first, as shown in
FIG. 1A
, an element isolating oxide film
101
a
and gate patterns
102
are formed on a semiconductor substrate
101
and a convex type alignment mark
103
is also formed thereon.
Next, as shown in
FIG. 1B
, an oxide film
104
′ having a thickness of, for example, 800 nm or so is deposited on an entire surface of the resulting semiconductor substrate by, for example, a chemical vapor deposition (CVD) technique. Then, by reflow, etchback, chemical-mechanical polishing (CMP) or the like, the oxide film
104
′ is flattened. As a result, a flat oxide film
104
is formed.
Thereafter, as shown in
FIG. 1C
, a photoresist
105
is coated on an entire surface of the substrate. Then, an exposure light
106
is radiated onto the photoresist
105
by a reduced projection type exposure apparatus through a contact-forming mask
107
disposed above the semiconductor substrate
101
and having a prescribed configuration. As a result of this, a contact opening portion
108
and an alignment mark opening portion
109
are simultaneously exposed. Then, the photoresist
105
is developed.
Subsequently, as shown in
FIG. 1D
, by the use of a dry etching technique, the portions of the oxide film
104
corresponding to the contact opening portion
108
and to the alignment mark opening portion
109
are removed to thereby open a contact hole
110
and simultaneously expose the alignment mark
103
.
Next, as shown in
FIG. 1E
, a polycrystalline silicon film
111
having a thickness of, for example, 800 nm or so is deposited and thereafter the polycrystalline silicon film
111
is etched back by isotropic etching. As a result of this, the polycrystalline silicon film
111
is buried into the contact hole
110
.
Then, as shown in
FIG. 1F
, a conductive layer
112
that consists of a WSi film having a thickness of, for example, 100 nm is deposited on an entire surface of the resulting substrate. And, a photoresist is coated on an entire surface of the resulting substrate. Then, an exposure light
114
is radiated onto the photoresist by the reduced projection type exposure apparatus through a wire-forming mask
115
disposed above the semiconductor substrate
101
. At this time, the wire-forming mask
115
has a light-shielding portion at only a region aligned with the contact hole
110
. And, by developing the photoresist, the photoresist
113
is caused to remain on a wiring layer forming predetermined region, e.g., the contact hole
110
.
Subsequently, using the photoresist
113
as a mask, the conductive layer
112
is etched by anisotropic dry etching. As a result of this, as shown in
FIG. 1G
, a wiring layer
112
′ connected to the contact hole
110
is formed. Simultaneously, the convex type alignment mark
103
is exposed.
Thereafter, although not shown, using the thus-exposed convex type alignment mark
103
as a basis, a mask is positionally aligned to thereby form an upper layer pattern.
However, in this conventional method for manufacturing a semiconductor device, when etching the conductive layer
112
, as shown in
FIG. 1G
, the convex type alignment mark
103
is inconveniently deformed. When the convex type alignment mark
103
is deformed, the precision with which the mask is positionally aligned becomes inconveniently decreased at the time of overlapping the upper layer pattern.
Also, in order to make it easy to detect an alignment mark, there has hitherto been proposed a method for enlarging a difference in level between the alignment mark and the semiconductor substrate (Japanese Patent Application Laid-Open No. Hei 1-149435).
FIGS. 2A
to
2
D are sectional views illustrating in the sequential step order a conventional method for manufacturing a semiconductor device that is described in Japanese Patent Application Laid-Open No. Hei 1-149435.
In the conventional manufacturing method disclosed in this Publication, first, as shown in
FIG. 2A
, a glue insulating film
42
is formed on a semiconductor substrate
41
and, on the insulating film
42
, a glue metal wiring layer
43
is formed as an alignment mark.
Next, as shown in
FIG. 2B
, an oxide film
44
is formed in such a way as to cover the glue metal wiring layer
43
and flattened. Thereafter, a photoresist
45
is coated onto an entire surface of the resulting substrate. And, simultaneously with the exposing of the contact hole, the glue metal wiring layer
43
and a portion surrounding it is exposed. Thereafter, the photoresist
45
is developed. As a result of this, the photoresist
45
aligned with the glue metal wiring
43
and its surrounding portion is removed.
Subsequently, as shown in
FIG. 2C
, the portion corresponding to the contact hole is etched and simultaneously the portions of the glue metal wiring layer
43
and its surrounding portion are etched to thereby expose an upper part of the glue metal wiring layer
43
from the oxide film
44
.
Thereafter, as shown in
FIG. 2D
, an upper metal wiring layer
46
is formed and a photoresist
47
is formed thereon. And, alignment is done by the use of a laser light or the like.
Further, in order to prevent an alignment mark from being damaged, there has hitherto been proposed a method for forming a concave type alignment mark (Japanese Patent Application Laid-Open No. Hei 5-36600).
FIGS. 3A
to
3
G are sectional views illustrating a conventional method for manufacturing a semiconductor device in the sequential step order that is described in Japanese Patent Application Laid-Open No. Hei 5-36600.
In the conventional manufacturing method disclosed in this Publication, first, as shown in
FIG. 3A
, concave type alignment marks
52
are formed at the surface of a semiconductor substrate
51
and then an etchback photoresist
53
is formed on an entire surface of the resulting substrate. The surface of this etchback photoresist
53
is flat and smooth. Also, the semiconductor substrate
51
and etchback photoresist
53
have approximately the same etching rate.
Next, as shown in
FIG. 3B
, a photosensitive resist
54
is coated on the etchback photoresist
53
. It is to be noted that on the etchback photoresist
53
there may be formed an electron beam resist.
Subsequently, as shown in
FIG. 3C
, a mask is provided at a prescribed region located above the alignment mark
52
, whereby as indicated by the arrow marks the photosensitive resist
54
is exposed with the use of an exposure light. In a case where an electron beam resist has been used instead of the photosensitive resist
54
, electron beams are radiated.
And, by developing the photosensitive resist
54
, as shown in
FIG. 3D
, the photosensitive resist
54
is caused to remain at a prescribed region located above the alignment marks
52
. At this time, the etchback photoresist
53
is non-photosensitive and therefore is not removed and remains. Further, in order to cause the photosensitive resist
54
that has remained to have the same etching rate as that of the semiconductor substrate
51
, the photosensitive resist
54
and the etchback pho
Chaudhuri Olik
Eaton Kurt
NEC Corporation
Young & Thompson
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