Method of protecting a circuit arrangement for processing data

Details Method of protecting a circuit arrangement for processing data Method of protecting a circuit arrangement for processing data

2001-11-13

2004-06-22

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C324S500000

Reexamination Certificate

active

06754606

ABSTRACT:

The invention relates to a method of protecting a circuit arrangement for processing data.
In circuit arrangements for processing data, particularly in microprocessors, for example, those used in chip cards—smart card controllers—scan tests are increasingly performed during the manufacturing control stage—the production tests—in addition to self-tests by a read-only memory integrated preferably in the microprocessor, also referred to as test ROM, so as to protect these circuit arrangements from errors. In accordance with known methods, arbitrary states can be established by means of a shift register chain in the memory cells, formed as flip-flops, of the data-processing circuit arrangement, thus particularly in microprocessors or preferably smart card controllers. This means that after activation of the scan test mode, the shift register chain is completely available and allows loading of arbitrary states in the flip-flops forming part of the shift register chain.
These states are specifically evaluated for testing the functional capability of the memory cells of the circuit arrangement loaded with these states.
However, it appears that this operating state can also be restored after the circuit arrangement has been manufactured for a specific operation and that this is not acceptable for reasons of security, because the security functions of the circuit arrangement can then be attacked in this way.
It is an object of the invention to provide a method by which such attacks of the security functions of the circuit arrangement are made impossible.

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