Method of propagation delay testing a level sensitive array logi

Details Method of propagation delay testing a level sensitive array logi Method of propagation delay testing a level sensitive array logi

1976-06-30

1977-12-13

Malzahn, David H.

Registers

Systems controlled by data bearing records

Time analysis

324 73AT, G06F 1100

Patent

active

040630803

ABSTRACT:
Propagation delay testing is performed on a generalized and modular logic system that contains embedded arrays and can be used as arithmetic/logical/control unit in a digital computer or data processing system. Each such unit can be composed of combinatorial logic and storage circuitry. The storage circuitry may be of two types, randomly arranged latches, or arrays of storage cells. In the organization presented here the latches are arranged such that they have the capability of performing scan-in/scan-out operations independently of system control. Using this scan capability, the method of the invention provides for the state of the storage latches to be preconditioned and independent of prior circuit history. Selected propagation paths are sensitized by patterns from an automated test generator or designer supplied patterns. By alternating selected inputs and by applying proper timing control, propagation delay indications through the selected paths are obtained to determine delay behavior of the logic system.

REFERENCES:
patent: 3659088 (1972-04-01), Bolsvert, Jr.
patent: 3714403 (1973-01-01), Ammann et al.
patent: 3784907 (1974-01-01), Eichelberger
E. Lindbloom et al. "Program For Determining Reset-On Time in Weighted Adaptive Test Patterns" IBM Tech. Discl. Bulletin, July 1972, pp. 399-400.
P. Goel "Testing of Random Logic" IBM Tech. Disc. Bulletin, vol. 16, No. July 1973, pp. 429-430.

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