Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-06-29
2001-07-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S001000
Reexamination Certificate
active
06266280
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method of programming nonvolatile semiconductor devices, and more particularly to a method of programming a NOR-type flash memory at low power, in which a channel programming technique based on a Fowler-Nordheim (F-N) tunneling effect is employed to program cells in the flash memory at low power and high speed and make a simultaneous random access operation for the cells possible.
2. Description of the Prior Art
Generally, because nonvolatile memories have the advantage that data stored therein is subjected to no loss even though power is interrupted, they are widely used for the storage of data in a PC Bios, Set-top Box, printer, network server, etc. Recently, the nonvolatile memories have often been used even in fields such as a digital camera and cellular phone.
Among the nonvolatile memories, flash memories of an electrically erasable programmable read only memory (EEPROM) type have a function of erasing data in all memory cells in a lump. Such flash memories are classified into a NAND-type flash memory wherein at least two memory cell transistors are connected in series to one bit line and a NOR-type flash memory wherein at least two memory cell transistors are connected in parallel to one bit line.
FIGS. 1
a
and
1
b
are cross-sectional views illustrating a conventional method of programming a NOR-type flash memory, wherein
FIG. 1
b
shows an initial state of one cell selected in a memory cell array and
FIG. 1
a
shows a state of the selected cell after it is programmed.
With reference to
FIGS. 1
a
and
1
b
, the flash memory comprises a floating gate
12
which is a first conductor layer formed on an insulating film (not shown). The insulating film is formed on an active area of a p-type silicon substrate
10
as a semiconductor substrate. A control gate
14
is formed over the floating gate
12
via an insulating film (not shown) The gates
12
and
14
are sequentially stacked in this manner. The flash memory further comprises a source S and drain D which are impurity-doped regions
16
formed by doping n-type impurities into portions of the active area in the neighborhood of edges of the stacked gates
12
and
14
. Here, the control gate
14
is connected to a word line and the drain D is connected to a bit line.
The above-mentioned flash memory has a stacked gate structure and is programmed in a hot-electron implantation manner. In the case where the memory cell is at an erased state as shown in
FIG. 1
b
, the floating gate
12
is filled with holes, thereby making a threshold voltage low in level. In the case where the memory cell is to be programmed as shown in
FIG. 1
a
, a high voltage of about 12V is applied to the control gate
14
, a voltage of 0V is applied to the source S and the half voltage of about 5V is applied to the drain D. As a result, a large amount of current flows from the source S to the drain D), resulting in hot electrons being generated in the neighborhood of edges of the drain D. The generated hot electrons are implanted into the floating gate
12
by the high voltage applied to the control gate
14
. Then, the threshold voltage is raised by the hot electrons implanted into the floating gate
12
, resulting in the memory cell being programmed.
FIG. 2
is a circuit diagram showing an array of the NOR-type flash memory in
FIGS. 1
a
and
1
b.
With reference to
FIG. 2
, most nonvolatile memories including the flash memory each have an array structure comprising a plurality of word lines WL
1
, WL
2
, . . . , Wln, a plurality of bit lines bit
1
, bit
2
, . . . , bitn and a common source line.
In the flash memory, cell threshold voltages are lowered by erasing information stored in all cells C
11
, C
12
, . . . , Cln, . . . Cnn. A desired cell to be programmed is selected among the memory cells and then subjected to a programming operation. If the selected memory cell has an address of 2,3 (row,column), the second word line WL
2
is selected and applied with 12V and the third bit line bit
3
is selected and applied with 5V. Also, 0V is applied to the common source line. Then, the cell C
23
is programmed in the above-mentioned hot-electron implantation manner.
FIGS. 3
a
and
3
b
are views illustrating a cell sensing operation of the NOR-type flash memory in
FIGS. 1
a
to
2
, wherein
FIG. 3
a
illustrates the operation of a sense amplifier
34
for sensing information from a programmed or erased cell. The sense amplifier
34
senses whether the associated memory cell is at a programmed state, on the basis of the fact that a programmed cell has a high threshold voltage level and an erased cell has a low threshold voltage level.
The sense amplifier
34
is adapted to perform the sensing operation in response to an output voltage Vmain from a cell
30
to be compared (referred to hereinafter as “comparison cell”) and a reference voltage Vref from a reference voltage generator
32
. As shown in
FIG. 3
b
, the sense amplifier
34
compares the output voltage Vmain from the comparison cell
30
with the reference voltage Vref from the reference voltage generator
32
and outputs the compared result Sout indicative of whether the comparison cell
30
is at a programmed state Vp or at an erased state Ve.
The above-mentioned flash memory is disadvantageous in that it requires a large amount of current consumption in performing the programming operation and is difficult to program a number of cells at the same time. Further, the entire programming speed is low because the programming operation can be performed only on a byte-by-byte basis or a word (16 bits)-by-word basis.
On the other hand, a data read operation is carried out by selecting a desired one of a number of word lines, applying a supply voltage Vcc to the selected word line, selecting a desired one of a number of bit lines and applying a low voltage of about 1V to the selected bit line. In the case where the associated cell is at the erased state, a current path is formed from the selected bit line to a ground voltage terminal through the cell, resulting in the bit line being subjected to a current leakage and thus falling in voltage level. In the case where the associated cell is at the programmed state, it is not turned on although the supply voltage Vcc is applied to the word line. As a result, the bit line does not fall to low in level and thus remains high in level. This high level voltage on the bit line is compared with the reference voltage Vref, as shown in
FIG. 3
b
, so that it can be read.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of programming a nonvolatile semiconductor device at low power, in which a programming operation is performed in an F-N tunneling manner instead of a hot-electron implantation manner to program cells in the semiconductor device at low power and program a number of cells among them at the same time to reduce the entire programming time.
In accordance with the present invention, in a method of programming a NOR-type flash memory which comprises a memory cell array composed of a plurality of memory cells, each of the memory cells having a transistor including a multi-layer stacked gate, drain and source, there is provided a method of programming a nonvolatile semiconductor device at low power, comprising the step of programming information in a selected one of the memory cells by applying a high voltage to the gate of the selected memory cell to induce a strong electric field from a semiconductor substrate, applying a ground voltage to the drain of the selected cell and allowing the source of the selected cell to float.
Preferably, the programming step may include the step of applying a desired voltage to the drains of nonselected ones of the memory cells not to program the nonselected memory cells, the desired voltage having half the level of the high voltage applied to the gate of the selected memory cell.
In a feature
Crompton Seager & Tufte LLC
Hyundai Electronics Industries Co,. Ltd.
Le Thong
Nelms David
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