Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2009-12-31
2011-11-08
Tran, Michael (Department: 2827)
Static information storage and retrieval
Floating gate
Multiple values
C365S185240
Reexamination Certificate
active
08054685
ABSTRACT:
A method of sequentially performing a LSB program operation and an MSB program operation of a nonvolatile memory device, wherein the nonvolatile memory device comprises multi-level memory cells each configured to store two pieces of bit information and page buffers each coupled to a bit line coupled with the memory cells and configured to comprise a first latch coupled to first and second nodes and a second latch coupled to third and fourth nodes, the method including inputting data of MSBs to the second and fourth nodes and setting data of the second and fourth nodes according to a state of data of LSBs stored in the memory cells, and precharging the bit line according to a combination of data stored in the first and second latches and performing the MSB program operation according to a state of a LSB program operation stored in the memory cells.
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patent: 2009/0161443 (2009-06-01), Yang et al.
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Notice of Allowance issued from Korean Intellectual Property Office on Feb. 24, 2011.
Hynix / Semiconductor Inc.
IP & T Group LLP
Tran Michael
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