Method of programming non-volatile semiconductor memory device

Details Method of programming non-volatile semiconductor memory device Method of programming non-volatile semiconductor memory device

2001-11-20

2003-09-02

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185270, C365S185050, C365S185280

Reexamination Certificate

active

06614688

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to a semiconductor memory device, and more specifically, is directed to a method of programming a non-volatile semiconductor memory device capable of cutting off a leakage current flowing through a parasitic MOS transistor formed between adjoining memory cells of the same row, and a leakage current flowing through a string select transistor.
BACKGROUND OF THE INVENTION
This application relies for priority upon Korean Patent Application No. 2000-083619, filed on Dec. 28, 2000, the contents of which are herein incorporated by reference in their entirety.
There is a need to electrically erase and program semiconductor memory devices without refreshing data stored within the semiconductor memory device. Also, there is a continuing need to increase storage capacity and integration level of the memory devices. A NAND-type flash memory device is one example of non-volatile memory devices that can provide mass storage capacity and a high integration level without refresh of data stored therein. Since such a flash memory is able to retain data even in power-off state, it has widely been used in electric apparatuses (e.g., mobile telephones, portable computers, Personal Digital Assistants, digital cameras, and so forth).
A non-volatile memory device such as a NAND-type flash memory includes electrically erasable and programmable read only memory cells, which are called “flash EEPROM cells”. Conventionally, a flash memory cell includes a cell transistor or a floating gate transistor. The transistor, which is formed at a pocket P-well area as a substrate, includes N-type source and drain regions spaced out a predetermined distance apart from each other, a floating gate located on a channel region between the source and drain regions to store charges, and a control gate located on the floating gate.
Referring now to
FIG. 12
, an array configuration of a conventional NAND-type flash memory device is illustrated. A memory cell array is formed at a pocket P-well area, and includes a plurality of cell strings
10
each corresponding to bitlines. The pocket P-well area is formed in an N-well area of a P-type semiconductor substrate (see FIG.
2
). For simplicity of the drawing, there are shown only two bitlines BL
0
and BL
1
and two cell strings
10
corresponding thereto. Each of the cell strings
10
is made of a string select transistor (SST) as a first select transistor, a ground select transistor (GST) as a second select transistor, and a plurality of flash EEPROMs (MCm (m=0-15)) serially coupled between the select transistors. SST and GST. The string select transistor SST has a drain coupled to a corresponding bitline, and a gate coupled to a string select line SSL. The ground select transistor GST has a source coupled to a common source line CSL, and a gate coupled to a ground select line GSL. The flash EEPROM cells MC
15
-MC
0
are serially coupled between a source of the string select transistor SSL and a drain of the ground select transistor GSL, and have gates coupled to corresponding wordlines WL
15
-WL
0
, respectively.
Initially, flash EEPROM cells of a memory cell array are erased to have a threshold voltage of, for example, −3 V. For programming the flash EEPROM cells, a high voltage Vpgm is applied to a selected wordline and a pass voltage Vpass is applied to an unselected wordline. Thus, a threshold voltage of a selected memory cell is boosted, while threshold voltages of the other (unselected) memory cells are not changed.
If it is desired to not program unselected flash EEPROM cells coupled to the selected wordline while programming selected memory cell(s) coupled to the same wordline, problems occur.
When a program voltage is applied to the selected wordline, the program voltage is applied to not only the selected flash EEPROM cell but also unselected flash EEPROM cells arranged along the same wordline. The unselected flash EEPROM cell coupled to the wordline, particularly, a flash EEPROM cell adjacent to the selected cell is programmed. Inadvertent programming of an unselected cell coupled to a selected wordline is called “program disturb”.
One of technologies for preventing the program disturb is a program inhibit method using a self-boosting scheme, which is disclosed in U.S. Pat. No. 5,677,873 entitled “METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICE TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN”, and U.S. Pat. No. 5,991,202 entitled “METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY”.
An operation timing view based upon the foregoing program inhibit method using the self-boosting scheme is illustrated in
FIG. 13. A
voltage of 0 V is applied to a gate of a ground select transistor GST, cutting off a ground path. A voltage of 0 V is applied to a selected bitline (e.g., BL
0
), and a power supply voltage VCC of 3.3 V or 5 V is applied to an unselected bitline (e.g., BL
1
). At the same time, the power supply voltage VCC is applied to a gate of a string select transistor SST coupled to a bitline BL
1
(see FIG.
12
), charging a source of the string select transistor SST (or a channel of a program inhibit cell transistor) up to VCC-Vth (here, Vth denotes a threshold voltage of the string select transistor SST). The string select transistor SST is substantially shut off. This interval is called “bitline setup interval”.
Then, a program voltage Vpgm is applied to a select wordline and a pass voltage Vpass is applied to unselect wordlines, boosting a channel voltage Vchannel of a program inhibit cell transistor. Fowler-Nordheim (F-N) tunneling is not created between a floating gate and a channel, so that the program inhibit cell transistor retains an initial erase state. This interval is called “program interval”. If programming the selected memory cell is completed, a discharge operation is carried out to discharge a potential of a bitline. For the bitline setup, program, and discharge intervals, a pocket PPWELL area and an N-well NWELL are biased with a ground voltage, as shown in FIG.
13
.
When the foregoing program inhibit method using the self-boosting scheme is employed on a flash memory device, unfortunately, one problem occurs. The higher the integration level of the flash memory device is, the narrower the spacing between adjoining signal lines is. This causes a signal line coupling through a parasitic capacitance (see
FIG. 12
) that is created between adjoining signal lines. For example, assume that a memory cell MC
15
adjacent to (or located beneath) the string select transistor SST is programmed. When a program voltage is applied to a select wordline WL
15
coupled to the memory cell MC
15
, a voltage (e.g., power supply voltage) of the string select line SSL is boosted higher than a power supply voltage VCC, due to a coupling to a select wordline WL
15
through a parasitic capacitance, as shown in FIG.
13
. The voltage boosting makes charges in the channel of the program inhibit cell transistor discharged to a bitline through a string select transistor (which is changed from a shut-off state to a turn-on state by the voltage boosting). In other words, the channel voltage Vchannel (or inhibit voltage Vinhibit) of the program inhibit cell transistor is lowered as much as &Dgr;V (determined by a coupling ratio of a wordline to a string select line and a program voltage) in proportion to the boosting voltage of the string select line SSL, as shown in FIG.
13
. Therefore, the program inhibit cell transistor is inadvertently programmed (i.e., program disturb occurs).
Another problem is caused by employing the foregoing program inhibit scheme. That is, “program disturb” occurs in a program inhibit flash EEPROM cell that is adjacent to a flash EEPROM cell to be programmed by a leakage current flowing through a parasitic MOS transistor. This will now be explained in detail hereinbelow.
With reference to
FIG. 14
illustrating a cross-sectional view of an array configuration taken along line a dotted line A-A&prim

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