Method of programming NAND-type flash memory

Details Method of programming NAND-type flash memory Method of programming NAND-type flash memory

2002-02-11

2003-12-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185180, C365S185290

Reexamination Certificate

active

06661707

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2001-07914, filed on Feb. 16, 2001, the contents of which are herein incorporated by reference in their entirety.
1. Field of the Invention
The present invention relates to a flash memory device and, more particularly, to a method of programming a flash memory device with a NAND-type cell array.
2. Background of the Invention
Flash memory devices are block or sector-erasable memory devices, and data readable/writable non-volatile memory devices. As one of the flash memory devices, a flash memory device with a NAND-type flash memory cell array (hereinafter referred to as “NAND flash”) benefits from high integration, in which memory cell strings composed of memory cells are serially connected to a bitline. A NAND flash having such a configuration is disclosed in the paper ISSCC 1995, pp. 128-129, published in 1995.
FIG. 1
is a diagram of a memory cell array as taught in the ISSCC 1995 paper. A plurality of memory cell strings are each connected to a plurality of bitlines.
FIG. 1
is transversed by wordlines WL
1
-WL
16
.
A unit cell string is associated with a single bitline intersecting a number of wordlines. For example, a unit cell string is composed of a string select transistor SST connected to bitline BL
1
, a ground select transistor GST connected to a common source line CSL, and a plurality of memory cells (or cell transistors) M
11
-M
161
serially coupled between the select transistors SST and GST. Gates of the memory cells M
11
-M
161
are each coupled to wordlines WL
1
-WL
16
.
Each memory cell is composed of a floating gate isolated from a channel region by a tunnel oxide layer (having a thickness of about 100 Å) interposed therebetween, and a flash EEPROM (electrically erasable and programmable read only memory) having a control gate stacked over the floating gate with an interlayer insulating layer interposed therebetween.
Memory cells are now compared, to illustrate a difference in their treatment.
FIG. 2A
is an equivalent circuit diagram of a selected memory cell in programming. Referring now to
FIG. 2A
, if a voltage Vcg is applied to a wordline coupled to a control gate, a voltage Vfg applied to a floating gate is determined by a coupling ratio of a capacitance Ci between the floating gate and the control gate to a capacitance Ct between the floating gate and the channel region.
Vfg=[Ct/
(
Ct+Ci
)]×
Vcg
  [FIG.
2
A, selected cell]
FIG. 2B
is an equivalent circuit diagram of an unselected memory cell in programming. Referring now to
FIG. 2B
, if a voltage Vcg is applied to an unselected cell, a voltage Vfg applied to a floating gate is determined by:
Vfg
=[(
Ci+Cch
)/(
2
Ci+Cch
)]×
Vcg
  [FIG.
2
B, unselected cell]
It will be noted that Vfg is different for selected and unselected cells.
FIG. 3A
is a table showing applied voltages used for program, erase, and read operations in the NAND flash of FIG.
1
.
FIG. 3B
shows the sequence of applying voltages in the prior art.
Referring to
FIGS. 1
,
3
A,
3
B, it is assumed that M
21
is a selected memory cell. Then 0V is applied to a selected bitline (e.g., BL
1
) and the ground select line GSL. A power supply voltage Vcc of about 3V is applied to a unselected bitline BL
2
and to a string select line SSL. A program voltage Vpgm of about 20V is applied to the selected wordline (in this case, WL
2
). And, a pass voltage Vpass of about 12V is applied to the unselected wordlines WL
1
, WL
3
-WL
16
.
The applied 0V is applied to a channel of the selected memory cell M
21
through the string select transistor SST
1
and the memory cell M
1
. A voltage difference between the floating gate and the channel results in F-N (Fowler-Nordheim) tunneling. Electrons are then moved from the channel region to the floating gate, enabling a threshold voltage to increase in 1V.
An erase operation is carried out with a wordline unit (or page unit; memory cells coupled to one wordline composes one page). Generally, memory cells coupled to all wordlines in a unit cell string are defined with a block unit (or sector unit), which is used as an elementary unit of the erase.
If 0V is applied to a selected wordline and an erase voltage Vers of about 24V is applied to a bulk area (separated with a block or sector unit), an inverse electric field to a program operation is formed, which moves electrons from the floating gate to the bulk area. As a result, the threshold voltage of the memory cell is changed to −3V.
The read operation utilizes the fact that a threshold voltage is changed according to a state of a selected memory cell (i.e., whether the selected memory cell is programmed or erased). When 0V is applied to a selected bitline, unselected wordlines, a string select line SSL, and a ground select line GSL, and 0V is applied to a selected wordline WL
2
, if a programmed cell is a programmed cell (off-cell), there is no current flowing through the memory cell. And, if the programmed cell is an erased cell (on-cell), a current flowing through the memory cell is generated. A voltage of a bitline reacting to whether a current flows or not according to the memory cell state is sensed to carry out a read operation.
An undesirable programming disturbance phenomenon occurs in a string program inhibit cell or a page program inhibit cell while programming a program cell. In this case, the “program cell” means a memory cell coupled to a selected bitline and a selected wordline; the “string program inhibit cell” means an unselected memory cell belonging to the same string cell as a memory cell (or selected memory cell) coupled to a selected bitline and an unselected wordline; and the “page inhibit cell” means an unselected memory cell coupled to an unselected bitline and a selected wordline or an unselected memory cell belonging to the same page as a selected memory cell.
The programming disturbance phenomenon is that, although such unselected memory cells should not be programmed while programming a selected wordline, they do not retain initial states; in other words, they also become programmed. This is because such unselected memory cells are connected to the selected wordline or a selected bitline from a standpoint of the otherwise desirable circuit configuration of FIG.
1
.
A characteristic of the programming disturbance phenomenon varies in accordance with intrinsic program or erase states of the program inhibit cells.
To prevent the phenomenon, after obtaining a set width of the pass voltage Vpass based upon the states of the program inhibit cells, a pass voltage is set and applied to a program operation in consideration of a worst case.
Setting the pass voltage changes a channel voltage, causing F-N tunneling contributing to the programming disturbance, because there is a voltage difference of 3V between threshold voltages of a programmed memory cell and an erased memory cell. That is, a channel voltage of the program inhibit cell is set to prevent F-N tunneling.
For example, a voltage of a floating gate is boosted by a program voltage Vpgm in a program inhibit cell M
22
coupled to a selected wordline WL
2
and an unselected bitline BL
2
. On the other hand, a channel region of a memory cell is isolated from an external voltage to be floated by 0V applied to GSL and Vcc applied to SSL. If Vpass and Vpgm are applied then, an overall capacitance (Cg) in a gate formed by the foregoing Ci and Ct (control gate+floating gate) can extract an equation “1/Cgate=1/Ci+1/Ct”. If the channel capacitance (Cch′) meets the following equation “Cch′=Cch+Cjnc (junction capacitance at a source and a drain)”, a voltage (Vch) induced to a channel of a page program inhibit cell M
22
is represented hereinbelow.
Vch=V
pass×(
Cg+Cch
′)×(
WL
number−1)+(
Cg/
(
Cg+Cch
′))×1
In the same page program inhibit cell as M
22
, Vch is formed to lower a strength of an electric field b

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