Method of programming electrically erasable programmable read-on

Details Method of programming electrically erasable programmable read-on Method of programming electrically erasable programmable read-on

1991-08-22

1994-03-15

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

36518909, 3072962, 307469, G11C 1140

Patent

active

052950956

ABSTRACT:
The apparent voltage used to program an EEPROM cell is increased by applying a negative voltage to the memory control gate of the sense transistor in the cell. This method is applicable to devices in which the substrate is negatively biased.

REFERENCES:
patent: 4388537 (1983-06-01), Kanuma
patent: 4884239 (1989-11-01), Ono et al.
T. Nakayama et al., "A5-U-only one-Transistor 256K EEPROM W. Page-Mode Erase," IEEE J. of S-S Ckts., vol. SC-24 #4, Aug. 1989, pp. 911-915.
R. James, "Elec, Rewr. Nonvol. Stor, Hav. Red Wr. vol., " IBM Tech. Discl. Bull, vol. 16 #2, Jul. 1973, pp. 690-691.
N. Anantha et al., "Elec. Eras. F-6 FET Memory Cell," IBM Tech. Discl. Bull., vol. 17 #8, Jan. 1975, pp. 2311-2313.
R. Dockerty, "Nonvolatile Mem. Array W. Single Famos Dev. Per Cell, " IBM Tech. Discl. Bull., vol. 17 #8, Jan. 1975, pp. 2314-2315.

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