Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2003-04-24
2004-07-27
Phan, Trong (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185240
Reexamination Certificate
active
06768673
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the field of non-volatile memory devices and, more particularly, to a method of storing data using a flash memory device, such as a dual cell electrically erasable and programmable memory device.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to increase the amount of data stored per unit area on an integrated circuit memory unit, such as a flash memory unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as core memory cells). For instance, a conventional dual cell memory device, such as a charge trapping dielectric flash memory device, can store data in a “double-bit” arrangement. That is, one bit (i.e., a binary data value have two states, such as a logical one and a logical zero) can be stored using a charge storing cell on a first “side” of the memory device and a second bit can be stored using a complimentary charge storing cell on a second “side” of the memory device.
Programming of such a memory device can be accomplished, for example, by hot electron injection. Hot electron injection involves “pulsing” the device by applying appropriate voltage potentials to each of a gate and a drain of the memory device for a specified duration. During the programming pulse, the source is typically grounded. Reading of the memory device can be accomplished by applying an appropriate voltage to each of the gate and the drain and comparing the drain to source current (as an indication of device threshold voltage) against a reference value to determine if the read charge trapping cell is in a programmed or an unprogrammed state.
Even though conventional charge trapping dielectric flash memory devices are capable of storing two single-bit binary data values per memory device, conventional charge trapping dielectric flash memory devices can suffer from data retention problems, especially over repeated program/erase cycles. Additionally, the “double-bit” data storage arrangement can result in read operation problems, such as complimentary bit disturb. Complimentary bit disturb most often arises when a programmed side a memory device effects the threshold voltage of the memory device during reading of an unprogrammed side of the memory device.
As a result, there is an ever increasing demand to store data in memory devices while increasing the data retention ability and reliability characteristics of the memory devices. There is also an ever increasing demand to lower the power consumed by the memory device.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is directed to a method of programming a dual cell memory device to store a single data value and of reading the data value. The memory device has a first charge storing cell and a second charge storing cell. The method includes storing a first amount of charge with the first charge storing cell, the first amount of charge corresponding to the data value and corresponding to a program state selected from a blank program level and a charged program level; storing a second amount of charge with the second charge storing cell, the second amount of charge corresponding to the data value and corresponding to the program state of the first charge storing cell; and reading one of the charge storing cells to determine the program state of each of the charge storing cells as an indication of the data value stored by the memory device.
According to another aspect of the invention, the invention is directed to a method of programming a dual cell memory device to store a single data value and of reading the data value. The memory device has a first charge storing cell and a second charge storing cell. The method includes storing a first amount of charge with the first charge storing cell, the first amount of charge corresponding to the data value and corresponding to a program state selected from a blank program level, a first charged program level, a second charged program level and a third charged program level, each program state being distinct from the other program states; storing a second amount of charge with the second charge storing cell, the second amount of charge corresponding to the data value and corresponding to the program state of the first charge storing cell; and reading one of the charge storing cells to determine the program state of each of the charge storing cells as an indication of the data value stored by the memory device.
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Hamilton Darlene
He Yi
Hsia Edward
Lee Mimi
Madhani Alykhan F.
Advanced Micro Devices , Inc.
Phan Trong
Renner , Otto, Boisselle & Sklar, LLP
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