Method of programming and/or verifying a threshold voltage level

Details Method of programming and/or verifying a threshold voltage level Method of programming and/or verifying a threshold voltage level

1997-07-09

1999-04-06

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518503, 36518524, G11C 1606

Patent

active

058927140

ABSTRACT:
A method of at least one of programming and verifying a threshold voltage of a nonvolatile memory cell. The memory cell includes a control gate, a floating gate, a drain, a source, and a channel region between the drain and the source. The method is a voltage-type programming compared to a current type programming. A first voltage, which varies in correspondence to each threshold level programming, is applied to the control gate, and second and third voltages are applied to the drain and the source, respectively, so that the channel region is turned off at an initial stage and charge carriers for the programming are transferred from the floating gate to the drain. A conductivity of the channel region is monitored during each threshold level programming. The application of at least one voltage among the first voltage, second voltage and third voltage is cut-off to stop the programming when the monitored conductivity reaches a reference value which may be constant for every threshold level to be programmed and/or verified.

REFERENCES:
patent: 5043940 (1991-08-01), Eliyahou
patent: 5386388 (1995-01-01), Atwood et al.
patent: 5422842 (1995-06-01), Cernea et al.
patent: 5426611 (1995-06-01), Maruyama
patent: 5452249 (1995-09-01), Miyamoto et al.
patent: 5513193 (1996-04-01), Hashimoto
patent: 5568426 (1996-10-01), Roohparvar et al.

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