Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-11-13
2003-01-28
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185270, C365S185280
Reexamination Certificate
active
06512696
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for programming and erasing a memory device, and more particularly to a method for programming and erasing a non-volatile memory device with a multi-layer gate insulating structure.
2. Description of the Prior Art
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications: A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
Semiconductor ROM devices, however, suffer from the disadvantage of not being electrically programmable memory devices. The programming of a ROM occurs during one of many steps in manufacturing, using special masks containing the data to be stored. Thus, the entire contents of a ROM must be determined before manufacturing. In addition, because ROM devices are programmed during manufacturing, the time delay before the finished product is available could be six weeks or more. The advantage, however, of using ROM for data storage is the low cost per device. However, the penalty is the inability to change the data once the masks are committed. If mistakes in the data programming are found they are typically very costly to correct. Any inventory that exists having incorrect data programming is instantly obsolete and probably cannot be used. In addition, extensive time delays are incurred because new masks must first be generated from scratch and the entire manufacturing process repeated. Also, the cost in savings with the use of ROM memories only exist if large quantities of ROM are produced.
Moving to EPROM semiconductor devices eliminates the necessity of mask programming the data but the complexity of the process increases drastically. In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacturing of these types of memory devices. An advantage of EPROM's is that they are electrically programmed, but for erasing, EPROM's require exposure to ultraviolet (UV) light. These devices are constructed with windows transparent to UV light to allow the die to be exposed for erasing; this must be performed before the device can be programmed. A major drawback to these devices is that they lack the ability to be electrically erased. In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.
Semiconductor EEPROM devices also involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the devices. The widespread use of EEPROM semiconductor memory has prompted much research focusing on constructing better memory cells. Active areas of research have focused on developing a memory cell that has improved performance characteristics such as shorter programming times, utilizing lower voltages for programming and reading, longer data retention times, shorter erasing times and smaller physical dimensions. One such area of research involves a memory cell that has an insulated gate.
Accordingly, it is the intention to develop a method of programming and erasing an EEPROM memory device, which can show the above improved performance characteristics, by utilizing superior properties of the memory cells.
SUMMARY OF THE INVENTION
It is an objective of the present invention to provide a method of programming a SNNNS type non-volatile memory device by using a channel hot electron injection to trap negative charges in an intermediate trapping layer under low applied voltages.
It is anther objective of the present invention to provide a method of erasing a SNNNS type non-volatile memory device by using channel hot hole injection to trap positive charges in an intermediate trapping layer under low applied voltages.
It is a further objective of the present invention to provide a method of programming a SNNNS type non-volatile memory device that is performed by using highly efficient channel hot electron injection to an intermediate trapping layer under predetermined applied voltages, such that a shorter programming time is provided.
It is still a further objective of the present invention to provide a method of erasing a SNNNS type non-volatile memory device that is performed by using highly efficient channel hot hole injection to an intermediate trapping layer under predetermined applied voltages, such that a shorter erasing time is provided.
It is yet a further objective of the present invention to provide a method of programming and erasing a SNNNS type non-volatile memory device, which can reduce power consumption of the memory device.
In order to achieve the above objectives, the present invention provides a method of programming and erasing a SNNNS type nonvolatile memory device. The SNNNS type non-volatile memory device comprises a semiconductor substrate with P type conductivity, a first diffusion region with N type conductivity, a second diffusion region with N type conductivity, a channel, a polysilicon gate and a stacked gate insulating layer including a bottom silicon nitride layer, an intermediate silicon nitride layer and a top silicon nitride layer. The first diffusion region is spaced from the second diffusion region and both of them formed underlying the surface of the semiconductor substrate. The channel is formed in the semiconductor substrate between the first diffusion region and the second diffusion region. The stacked gate insulating layer is formed between the polysilicon gate and the semiconductor substrate. The programming operation is performed by applying a first programming voltage to the polysilicon gate and a second programming voltage smaller than the first programming voltage to the first diffusion region and grounding the second diffusion region and the semiconductor substrate, thereby injecting channel hot electrons to the intermediate silicon nitride layer to program the memory cell to a predetermined state. The erasing operation is performed by applying a first erasing voltage to the polysilicon gate and a second erasing voltage to the first diffusion region and grounding the second diffusion region and the semiconductor substrate. The first and second erasing voltages are sufficient to cause channel hot holes to inject to the intermediate silicon nitride layer to perform the erasing operation.
REFERENCES:
patent: 5535158 (1996-07-01), Yamagata
patent: 6285596 (2001-09-01), Miura et al.
patent: 6363012 (2002-03-01), Lin et al.
Fan Tso-Hung
Lu Tao-Cheng
Pan Samuel
Wang Ta-Hui
Lam David
Macronix International Co. Ltd.
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