Method of programming and erasing a non-volatile memory array

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S218000, C365S189011

Reexamination Certificate

active

07869282

ABSTRACT:
A method of processing an array of non-volatile memory cells to program or erase the same, by applying a voltage to the same through a program and verify pulse application circuit. The process includes a first step of selecting a voltage to be applied. Then, the maximum number of memory cells that can be processed simultaneously is determined, based on the selected voltage and characteristics of the memory cells and the circuit. The array is divided into processing groups, each group having a number of cells less than or equal to the maximum determined number. Finally, the voltage is applied to the cells.

REFERENCES:
patent: 5345583 (1994-09-01), Davis
patent: 6396741 (2002-05-01), Bloom et al.
patent: 6937521 (2005-08-01), Avni et al.
patent: 7512002 (2009-03-01), Kim
patent: 7599225 (2009-10-01), Loh et al.

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