Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-12-19
2004-02-03
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S189090
Reexamination Certificate
active
06687159
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of programming a plurality of memory cells connected in parallel, and more particularly to a circuit for programming a plurality of memory cells, which memory cells are connected, through column decoder means, to a program voltage reference provided by a charge pump circuit, and to a second voltage reference, and which have their gate terminals connected together and to a word line, and in addition to a method and a circuit for programming Flash memory cells, the detailed description hereinafter covering this field of application for convenience of explanation only.
2. Description of the Related Art
As is well known, one of the modes for programming a flash memory cell involves use of a circuit adapted to generate a voltage ramp on the cell gate terminal.
At steady state, the value of the threshold voltage of a cell follows the ramp slope and is accompanied by a degree of overdrive due to the varying demand for voltage from individual cells with respect to the voltage provided by the circuit, while the demand for current at the drain terminal of the cell remains constant.
Setting the slope of the voltage ramp also sets the current demand from the individual cells. All the above restrains, however, the number of cells that can be programmed in parallel.
In particular, the voltage to be applied to the drain terminal of a cell is provided by a suitable charge pump circuit which, due to area and power restrictions, can only supply a limited amount of current (a few mA) reflecting on a maximum number of cells that can be programmed in parallel.
In order to program a larger number of cells than the maximum allowed by the charge pump circuit capabilities, it has been common practice to complete the programming operation as two distinct steps, namely:
a first step, in which a number of cells equal to the allowed maximum are programmed; and
a second step, in which the surplus cells are programmed.
In practice, the second programming step has an inefficiency in that the charge pump circuit is potentially capable of supplying a much larger current than that used by the surplus cells, the number of these cells being smaller than the maximum number of programmable cells for which the charge pump circuit has been set.
Also, the time required for splitting the operation into the two steps delays the programming operation.
BRIEF SUMMARY OF THE INVENTION
An embodiment of the invention is directed to a memory cell programming method whereby the use of a suitable charge pump circuit can be optimized and the shortcomings of prior programming methods overcome.
The memory cell programming method provides for automatically adjusting the slope of the voltage ramp applied to the memory cells to suit load demand, using a loop system that includes the cells to be programmed.
The method of programming a plurality of memory cells connected in parallel between first and second supply references and having their gate terminals connected together and, through row decoding means, also connected to an output terminal of an operational amplifier adapted to generate a word voltage signal, said first voltage reference being provided by a charge pump circuit, uses a program loop that includes said cells to be programmed and said operational amplifier, such that said charge pump circuit will output a voltage ramp whose slope is a function of the cell demand.
Another embodiment is directed to a circuit for programming a plurality of memory cells connected, through a plurality of column decode switches, to a program voltage reference provided by a charge pump circuit, and connected to a second voltage reference, with the cell gate terminals sharing connection to a word line, the circuit comprising an operational amplifier having a first input terminal connected to said program voltage reference, a second input terminal connected to an external voltage reference, and an output terminal connected, through an additional row switch, to said word line to provide a word voltage signal, said operational amplifier being, together with said cells, connected in a program loop able to adjust the slope of an output voltage ramp from said charge pump circuit to suit the cell demand.
REFERENCES:
patent: 4797856 (1989-01-01), Lee et al.
patent: 6111791 (2000-08-01), Ghilardelli
De Sandre Guido
Guaitini Giovanni
Iezzi David
Pasotti Marco
Poles Marco
Jorgenson Lisa K.
Le Vu A.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tarleton E. Russell
LandOfFree
Method of programming a plurality of memory cells connected... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of programming a plurality of memory cells connected..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of programming a plurality of memory cells connected... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3328555