Method of programming a non-volatile memory cell to...

Details Method of programming a non-volatile memory cell to... Method of programming a non-volatile memory cell to...

2006-09-05

2006-09-05

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185190

Reexamination Certificate

active

07102930

ABSTRACT:
A method to eliminate program deceleration and to enhance the resistance to program disturbance of a non-volatile floating gate memory cell is disclosed. This method eliminates or minimizes the impact of the hole displacement current. This can be done, for example, by increasing the rise time of the high programming voltage applied to the high voltage terminal. Alternatively, the transistor of the non-volatile floating gate memory cell can be turned off until the voltage applied to the high voltage terminal has reached the programming voltage. This can be done, for example by delaying the voltage applied to either the low voltage terminal or to the control gate to turn on the transistor until the voltage at the high voltage terminal has past the ramp up voltage and has reached a level programming voltage.

REFERENCES:
patent: 4434478 (1984-02-01), Cook et al.
patent: 5029130 (1991-07-01), Yeh
patent: 6040598 (2000-03-01), Nakayama et al.
patent: 6091636 (2000-07-01), Liu et al.
patent: 6172908 (2001-01-01), Cappelletti et al.

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