Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-11-27
2002-05-21
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170
Reexamination Certificate
active
06392929
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates Generally to a method of programming a flash memory cell, and more particularly to, a method, of programming a flash memory cell which can significantly reduce a programming current per cell to thus improve reliability and throughput of a device, in such a manner that one voltage of the voltages applied to a gate terminal and a drain terminal, which are applied when a flash memory device is programmed, is maintained at a given voltage level, while adjusting the other voltage of the voltages applied to the gate and the drain, by more than two steps.
2. Description of the Prior Art
As can be seen from
FIG. 1
, in a general stack gate-type flash memory cell, a tunnel oxide film
12
is formed at a selected region on a semiconductor substrate
11
, and a floating gate
13
, a dielectric film
14
and a control gate
15
are stacked thereon. Also, a source
16
and a drain
17
are formed at a given region on the semiconductor substrate
11
.
In order to program the above-mentioned flash memory cell, electrons must be injected into the floating gate by hot carrier injection method. For this, a high voltage must be applied to the control gate, in order to apply a voltage more than a given threshold voltage to the drain and induce thus generated electrons into the floating gate. On the other hand, the source and the substrate must be maintained at a ground potential.
However, as the cell size is reduced, the length of channel is shortened and the channel current is also rapidly increased when the programming operation is performed. Thus, it is very difficult to design the drain pump circuit that keeps the drain voltage at an appropriate value. In other words, the size of the transistor within the pump circuit must be greater and the degree of control in the process becomes degraded.
FIG. 2
shows a waveform of the voltages applied to the gate and drain terminals upon programming of the conventional flash memory cell. As shown, if a high voltage (about 9V) is applied to the gate from the beginning for performing the programming, as shown in
FIG. 2
, the drain voltage will not withstand the programming peak current because it will become greater, as shown in FIG.
3
. Therefore, the drain voltage will be reduced, as shown in FIG.
4
. Thus, the programming time will be extended unlimitedly, resulting in failure of the programming. Also, this causes a serious problem at the present time when a flash memory cell for use in a low voltage is widely used.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method of programming a flash memory cell capable of reducing a programming current per cell, thus improving reliability and throughput of a device.
In order to accomplish the above object, a method of programming a flash memory cell according to the present invention, which is performed applying a given voltage a gate and a drain and maintaining a source and a substrate at a ground potential is characterized in that it variably applies a given voltage, with two or more steps, to one of the gate and drain terminals while applying a given voltage to the other of the gate and drain terminals.
REFERENCES:
patent: 5943260 (1999-08-01), Hirakawa
patent: 6014330 (2000-01-01), Endoh et al.
Kim Min Kyu
Kim Tae Kyu
Lee Ju Yeab
Park Sheung Hee
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hyundai Electronics Industries Co,. Ltd.
Le Vu A.
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