Static information storage and retrieval – Floating gate – Particular connection
Patent
1996-08-09
2000-03-28
Zarabian, A.
Static information storage and retrieval
Floating gate
Particular connection
36518514, 36518518, G11C 1134
Patent
active
060440155
ABSTRACT:
The present invention is a method for programming SSI cells or an array of said cells. The method achieves very fast programming while consuming only a very small amount of power, which paves the way for new applications such as battery-operated systems, page-mode programming for very high data throughput. The method also allows for the bitline voltage to be increased internally on the chip in order to circumvent the efficiency decrease associated with supply voltage scaling. By exploring the SSI mechanism in the subthreshold regime, an optimum value for the CG voltage is found for which the gate current is no longer maximized, but the energy consumed from the power supply is minimized and the injection efficiency during programming is maximized. The programming of a memory cell in this regime, where the gate current is a very steep function of the CG voltage, is, however, still achieved in a few microseconds while consuming only a very small cell current in the range of nanoamperes. This allows an entire wordline in the array to be programmed simultaneously, even if the supply voltage is scaled down to 3.3V or below. This possibility, combined with a physical programming time per cell which is still very short, realizes an effective programming time in the order of 20 ns/byte for a 1 Mbit device, which corresponds to a maximum programming transfer rate of 50 Mbyte/s. State-of-the-art Flash memories typically show a transfer rate in the order of 20-300 Kbyte/s during programming which is 2 to 3 orders of magnitude slower than in the case of the present invention. Therefore, the method of the present invention with the accompanying programming scheme represents a substantial improvement in terms of high-speed-oriented as well as low-power-oriented applications. It is important to mention here that optimizing the injection efficiency instead of the gate current itself, is not a straightforward solution for next generation Flash memories, since the gate current is much more difficult to control due to the steepness of the subthreshold characteristic of the MOS device.
REFERENCES:
patent: 5029130 (1991-07-01), Yeh
patent: 5042009 (1991-08-01), Kazerounian et al.
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5212541 (1993-05-01), Bergemont
patent: 5235544 (1993-08-01), Caywood
patent: 5257225 (1993-10-01), Lee
patent: 5280446 (1994-01-01), Ma et al.
R, Kazerounian et al, 1988 IEDM, "ASV High Den. Poly-Poly Erase Flash EPROM Cell," pp 436-439.
J, Van Houdt et al, "ASVl3.3v Compat.Flash E.sup.2 PROM Cell . . .," 1993 Nonvol, Mem. Tech. Rev., pp 54-57.
J, Van Houdt et al., "HIMOS-A High EFF. Flash E.sup.2 PROM Cell . . .," IEEE Trans. On Elec, Dev., vol. 40, Dec. #13 1993, pp. 2255-2263.
J, Van Houdt et al., "A5V Compatible Flash EEPROM Cell . . .," IEEE Trans. on Comp, PRG & MFG Tech, PT, A, vol. 17#3, Sep. 1994, pp. 380-389.
J. Van Houdt et al., "Optimization of a Submicron HIMOS Flash E.sup.2 PROM . . . ," 9--13, 16-1993, 23.sup.rd Eur. S. S. Dev. Res. Conf., pp. 381-384.
D. Wellekens et al., "Write/Erase Degradation amd Disturb. Effects . . . ," Oct 4-7, 1994, 5.sup.th Eur. Sym. on Rel. of Elec, Dev., (no page nos.).
Deferm Ludo
Groeseneken Guido
Haspeslagh Luc
Maes Herman
Van Houdt Jan F.
IMEC vzw
Zarabian A.
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