Fishing – trapping – and vermin destroying
Patent
1995-04-21
1996-02-27
Thomas, Tom
Fishing, trapping, and vermin destroying
437195, H01L 218246
Patent
active
054948428
ABSTRACT:
A CMOS ROM is fabricated and programmed using a two-metal fabrication process which is substantially equivalent to a conventional CMOS polysilicon gate manufacturing technique so that the CMOS ROM is advantageously fabricated in the same process steps that are used to fabricate the other, non-ROM circuits on an integrated circuit chip. In this method, multiple bit-lines in a first metal layer are formed which overlie a substrate containing the array of transistors. The bit-lines are connected to drain regions of the transistors. A dielectric insulating layer is formed over the substrate and the bit-lines and the dielectric insulating layer is perforated by vias which allow connecting to the first metal layer. Multiple word-lines and multiple reference voltage lines are formed in a second metal layer overlying the dielectric insulating layer. Either a word-line or a reference voltage line is programmably selected to connect to the gate of a transistor for each transistor of the multiple transistors.
REFERENCES:
patent: 4326329 (1982-04-01), McElroy
patent: 4384399 (1983-05-01), Kuo
patent: 4390971 (1983-06-01), Kuo
Koestner Ken John
National Semiconductor Corporation
Thomas Tom
LandOfFree
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