Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
1998-07-30
2001-05-01
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S840000, C029S846000, C174S260000, C228S179100, C228S180210
Reexamination Certificate
active
06223429
ABSTRACT:
TECHNICAL FILED
This invention relates to a semiconductor device suited for connecting and packaging semiconductor elements on a wiring-circuit board (motherboard) through connectors, a wiring board for mounting semiconductors which is used for fabricating the semiconductor device, and a process for fabricating the semiconductor device.
More particularly, the present invention provides a semiconductor device that enables high-density packaging, is inexpensive and has a high reliability, and a process for its fabrication.
BACKGROUND ART
In recent years, as a method by which semiconductor elements having connecting terminals in a large number are connected and packaged in a high density on a wiring-circuit board (motherboard), a BGA (ball grid array) package of an OMPAC (overmolded packaging) system has been developed and is being put into practical use, according to which chips are mounted on an organic wiring board, pads on the chips are connected to connecting terminals on the side of the organic wiring board by gold-wire wire bonding, thereafter the whole semiconductor chips are covered with an organic insulating sealing material, and solder balls are arranged in arrays on the back of the organic wiring board to provide external terminals.
This structure can make the number of external terminals larger per unit area than conventional QFPs having a structure wherein chips are mounted on a metal lead frame and gold-wire wire bonding is carried out, thereafter the whole is sealed, and the external terminals are cut and formed so as to extend out of the sides of sealed portions. This has a characteristic feature that surface-mounted packaging on the motherboard by solder reflowing can be carried out with ease. However, since this requires gold-wire bonding, the size of semiconductor pads to be connected must be limited to about 80 &mgr;m and also a certain distance must be ensured between the pad and the wiring terminal. Accordingly, its external size can not help being as large as 40 mm square or more in order to form a BGA package having i/o terminals of 500 pins or more. This structure has had a limit for situations a needing much more pins and on packaging on the motherboard in a higher density.
Meanwhile, in order to meet the need for higher-density packaging of semiconductor chips each having 500 pins or more, a flip-chip bonding system is proposed (C
4
) in which metal plating for various barriers is applied to bonding pads of a semiconductor chip and thereafter solder bumps are formed, followed by heat-melt face-down bonding to the terminals on the side of the wiring board through the bumps. Application of this system is partly put forward in ceramic substrates. However, it is forecasted that the process up to the formation of solder bumps on the pads of the semiconductor chip has so many steps as to result in a very high cost of semiconductor chips, that the stress due to temperature cycling is concentrated on solder bumps unless the gap between the chip surface and the wiring board is filled with resin, that the processing and management of such filling with resin are troublesome, and that an attempt to use it to connect bumps to the organic wiring board may result in greater difference in coefficient of linear expansion between bumps and chips to make the stress greater. Accordingly, the flip-chip bonding of i/o terminals of 500 pins or more is not actually available at present.
Meanwhile, a method is proposed in which gold wires are wire-bonded to the bonding pads of a semiconductor chip and are cut at positions close to necks so that gold bumps can be formed on chips at a lower cost (i.e., stud bumps). However, in order to connect and package such chips on the wiring board by face-down bonding, it is essential to use a process in which an organic conductive adhesive is coated on the stud bumps and, after connection and curing, the gap between the chip surface and the wiring board is filled with resin. Also, there remains a problem that the process has a large number of steps since it requires the step of gold-wire bonding for each chip, and also that the size of the pads of chips is limited to 80 &mgr;m square and can not be made larger than that.
DISCLOSURE OF THE INVENTION
The present invention is intended to solve the problems of the prior art, and to provide a semiconductor device that is constituted using inexpensive chips having not gone through any bump formation process and using a relatively inexpensive organic high-density wiring board, can achieve high-density packaging through a simpler process and also has a high reliability, and a process for its fabrication.
Accordingly, the present invention provides semiconductor devices described in the following (1) to (3), a wiring board described in (4), and fabrication processes described in (5) to (7).
(1) A semiconductor device comprising a semiconductor chip face-down connected and mounted on a wiring board, wherein the semiconductor chip has a connecting pad which is concave lower than the surface of a passivation film of the chip, and the wiring board is provided at its connecting terminal with a metal bump which projects higher than at least the wiring portion; the connecting pad of the semiconductor chip and the metal bump of the connecting terminal of the wiring board are joined through, and the whole or part of the semiconductor chip surface and its opposing wiring board surface are adhesion-fixed with, an organic, anisotropic conductive adhesive material.
(2) In the semiconductor device described in the above (1), the semiconductor chip has a connecting pad which is concave lower than the surface of a passivation film of the chip, and the wiring board is provided at its connecting terminal with a metal bump which has a diameter smaller than the connecting pad of the semiconductor chip and is projected at a level identical to or higher than the depth of the pad; the connecting pad of the semiconductor chip and the metal bump of the connecting terminal of the wiring board are joined through, and the whole of the semiconductor chip surface and its opposing wiring board surface are adhesion-fixed with, an organic, anisotropic conductive adhesive material, the whole or at least an edge of the back of the semiconductor chip is covered with an insulating organic sealing material, and an external terminal is provided in a matrix on the back of the wiring board.
(3) In the semiconductor device described in the above (1), the organic, anisotropic conductive adhesive material is an anisotropic conductive adhesive film having a double-layer structure comprised of a layer formed of an organic matrix only or an organic matrix with inorganic filler particles dispersed therein and a layer formed of an organic matrix with conductive particles dispersed therein; the layer formed of an organic matrix only or an organic matrix with inorganic filler particles dispersed therein is provided on the side coming into contact with the semiconductor chip surface, and the layer formed of an organic matrix with conductive particles dispersed therein is provided on the connecting terminal side of the wiring board.
(4) A wiring board for mounting a semiconductor thereon, used in the semiconductor device of the present invention, comprising:
a metal bump which is projected higher than at least the wiring portion, provided at the connecting terminal on one surface of the wiring board;
an organic, anisotropic conductive adhesive material for face-down bonding and adhesion-fixing the semiconductor chip, provided at the part including at least the metal bump and opposing to the semiconductor chip surface; and
an external terminal having conduction to the connecting terminal, provided on the other surface of the wiring board.
The projected metal bump of this wiring board for mounting a semiconductor thereon may preferably be formed in a single-layer or multiple-layer construction of a metal or alloy selected from Cu, Cr, Ni, Pd, Au and a PbSn solder.
(5) A process for fabricating a semiconductor device, comprising the steps of:
forming a
Inoue Fumio
Kaneda Aizou
Kojima Kazuyoshi
Nagai Akira
Ohata Hiroto
Arbes Carl J.
Hitachi Chemical Company Ltd.
Pennie & Edmonds LLP
LandOfFree
Method of production of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of production of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of production of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2558376