Method of producing the gate electrode of a field effect transis

Details Method of producing the gate electrode of a field effect transis Method of producing the gate electrode of a field effect transis

1987-11-19

1989-08-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437912, 437187, 437184, 437176, 437177, 357 15, 357 22, H01L 2144

Patent

active

048596183

ABSTRACT:
A method of forming a self-aligned gate electrode of a field effect transistor, in which a resist pattern is formed on a substrate by lithography, an ion-implanted layer in the substrate at the side of the resist is formed by ion implantation, an insulating film is formed on the substrate by electron cyclotron resonance plasma chemical vapor deposition, the resist pattern and a part of the insulating film on the resist pattern removed by lift-off to thereby form an insulating pattern with an opening, the substrate annealed to activate said ion-implanted layer and a gate electrode formed in the opening by a spacer lift-off method.

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Matsuo et al., "Low Temperature Chemical Vapor Deposition Method Utilizing an Electron Cyclotron Resonance Plasma", Jap. J. of Appl. Phys., vol. 22, No. 4, Apr. 1983, pp. L210-L212.
Codella et al., "GaAs LDD E-MESFET For Ultra-High Speed Logic", IBM Technical Disclosure Bulletin, vol. 26, No. 4, Sep. 1983, pp. 1988-1989.
Yamasaki et al., "GaAs LSI-Directed MESFET's with Self-Aligned Implantation for N.sup.+ -Layer Technology (SAINT)", IEEE Trans. on Electron Devices, vol. ED-29, No. 11, Nov. 1982, pp. 1772-1777.
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