Method of producing semiconductor integrated circuit device incl

Details Method of producing semiconductor integrated circuit device incl Method of producing semiconductor integrated circuit device incl

1988-11-08

1990-05-22

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 31, 437 59, 437 41, 437162, 357 43, 357 59, H01L 21265

Patent

active

049277766

ABSTRACT:
A method of producing an integrated circuit device having a bipolar transistor and P-channel and N-channel MOS transistors (Bi-CMOS IC) is disclosed. This method includes the steps of forming a collector contact hole, depositing a polycrystalline silicon layer after formation of the collector contact hole, and diffusing impurities through the polycrystalline silicon layer into a collector region through the collector contact hole to form a collector contact region. The polycrystalline silicon layer doped with impurities is employed as a collector electrode and gate electrodes. The impurities in the collector contact region are re-diffused into the collector region by the subsequent heat treatments used in forming an emitter region and source and drain regions of the respective MOS transistors. A Bi-CMOS IC in which the collector resistance of the bipolar transistor is lowered is thereby produced without a great increase in manufacturing steps.

REFERENCES:
patent: 4484388 (1984-11-01), Iwasaki
patent: 4536945 (1985-08-01), Gray
patent: 4637125 (1987-01-01), Iwasaki

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