Method of producing semiconductor device layer layout

Details Method of producing semiconductor device layer layout Method of producing semiconductor device layer layout

1994-06-08

1996-03-12

Fourson, George

Fishing, trapping, and vermin destroying

437 50, 437 51, 15665911, H01L 2100

Patent

active

054985790

ABSTRACT:
A method of enhancing the lithographic resolution of randomly laid out isolated structures is disclosed. A first mask comprises an active layer with isolated features such as gates. Portions of the active layer have a reduced dimension typical of periodic structures. The first mask additionally has complementary features provided along side the reduced active features to provide periodicity. In this way, the resolution of the lithographic process is enhanced, and other enhanced resolution technologies additionally can be used to best advantage to form a patterned photosensitive layer having isolated features of reduced width. The photosensitive layer is then exposed to a second mask which exposes the complementary features so that they are removed from the latent image in the photosensitive layer. This second exposure also further improves resolution by enhancing the contrast between exposed and unexposed regions. A method is disclosed for automatically providing random logic device layouts having the complementary features, as well as for providing a layout for the second mask.

REFERENCES:
patent: 4895780 (1990-01-01), Nissan-Cohen et al.
patent: 5308741 (1994-05-01), Kemp
M. Helm, W. Kavanaugh, B. K. Liew, C. Petti, A. Stolmeijer, M. Ben-tzur, J. Bornstein, J. Lilygren, W. Ting, P. Trammel, J. Allan, G. Gray, M. Hartranft, S. Radigan, J. K. Shanmugan, R. Shrivastava, "A Low Cost Microprocessor Compatible, 18.4 .mu.m.sup.2, 6-T Bulk Cell Technology for High Speed SRAMS", Cypress Semiconductor Corp., pp. 65-66, 1993 Symposium On VLSI Technology Digest of Technical Papers, May 17-19, 1993, The Japan Society of Applied Physics and The IEEE Electron Devices Society.

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