Method of producing low thermal budget high dielectric...

Details Method of producing low thermal budget high dielectric... Method of producing low thermal budget high dielectric...

2001-06-25

2003-09-16

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

C438S397000, C438S399000, C438S776000, C438S254000, C438S777000, C438S253000

Reexamination Certificate

active

06620702

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to processing methods used for processing high dielectric constant metal oxide films and more particularly to methods with lower overall thermal budgets such that smaller generations of structures e.g., 0.15 micron may be reliably manufactured.
BACKGROUND OF THE INVENTION
The current trend of memory fabrication process for an integrated circuit includes increasing the storage density and the data storage amount on a single chip. A higher density provides a memory with a more compact storage. In addition, storing data on single chip is more economical compared to storing the equivalent amount of data on multiple chips. The density of integrated circuit can be increased via shrinkage of structures, for example, conductive lines or transistor gate, and reduction of spaces between structures. In the fabrication of integrated circuit, the shrinkage of circuit structure can be treated as a reduction of design rule.
The reduction of design rule results in a reduced substrate surface area, and consequently, the available area for fabricating the storage capacitor of a dynamic random access memory (DRAM) device is restricted. This limits the storage capacitance of the DRAM. The limitation of storage capacitance leads to problems such as mechanical deterioration and leakage current or even potential loss caused by larger dielectric susceptibility. Furthermore, the loss of storage charges caused by larger dielectric susceptibility may result in a more frequent refresh cycles. While refreshing, data accesses such as read and write operations can not be processed. Thus, a frequent refresh cycle requires a more complex data access scheme or a more sensitive charge sense amplifier. To increase the capacitance of a capacitor and to resolve the problems mentioned above, a three-dimensional capacitor has been developed. However, considerations of yield and throughput make this kind of capacitor structure complex and difficult to fabricate.
In addition to a three-dimensional capacitor, approaches including minimizing the thickness of the dielectric layer and using a dielectric layer with high dielectric constant can also achieve the objective of increasing capacitance. Many approaches have been tried using a dielectric layer with a high dielectric constant. For example, tantalum oxide (Ta
2
O
5
) with a dielectric constant three times larger than silicon nitride has been widely applied.
Dielectric films with dielectric constants higher than SiN have become necessary for scaling down dimensions in DRAM devices. The Ta
2
O
5
dielectric film is one of the better known and well-studied materials meeting this requirement. One of the more feasible approaches in forming the type of capacitor structure required in DRAM is by the application of a Ta2O5 dielectric film on a hemispherical grain (HSG) surfaced 3-dimensional bottom electrode.
One major problem in employing tantalum oxide is the very significant leakage current. Leakage current is induced by mutual interaction between the tantalum oxide layer and a bottom electrode. Forming an oxide layer or a nitride layer acts between the tantalum oxide layer and a bottom electrode acts to block the mutual interaction, reducing leakage current. It is known that the dielectric layer is formed as a thin film between the bottom electrode and the top electrode.
Although it has been found that the Ta
2
O
5
metal-insulator-semiconductor (MIS) can meet the requirements in terms of capacitance density and cell size, a major challenge remains in finding ways to reduce the thermal budget (i.e., the integral of device temperature T (t) over a fixed period of time) in processing the Ta
2
O
5
MIS capacitor as structure size diminishes to 0.15 microns and beyond. C As a result, processing methods that can be performed more quickly and at lower temperatures are critical in future DRAM processing.
For example, in the case of capacitors and MOS transistors, the high dielectric metal oxide film is normally formed on a silicon surface or a nitrided silicon surface, and a high temperature oxygen anneal can cause oxygen to diffuse through the dielectric and form undesired silicon dioxide at the metal oxide/silicon nitride and/or at the silicon nitride/poly interfaces. It is to be appreciated that silicon dioxide formation at these interfaces will create a low dielectric constant film in series with the high dielectric metal oxide film thereby reducing the effective capacitance of the film.
As an example of a high thermal budget prior art process, reference is made to
FIG. 1
where a flow diagram (
10
) depicts the prior art process of forming a Ta
2
O
5
MIS capacitor where an HSG crown is formed on bottom electrode in (
12
); followed by a remote thermal nitridation (
14
) at temperatures of about 800 to about 1000° C. to form a thin SiN barrier layer between the HSG surface and the subsequently deposited Ta
2
O
5
film; deposition of a Ta
2
O
5
film (
16
) at a temperature less than about 450° C.; followed by a thermal anneal (
18
) at temperatures from about 800 to 1000° C. in the presence of oxygen; and finally a chemical vapor deposition (CVD) (
20
) of TiN at about 680° C.
It is therefore an object of the present invention to provide low temperature processes with a reduced thermal budget that may be used in the production of deposited metal oxide dielectric film thereby improving the interface characteristics and electrical properties of a deposited metal oxide dielectric films and making them useable in smaller generations of integrated circuit structures.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for reducing a thermal budget in a semiconductor manufacturing process including in one embodiment: forming a hemispherical surface crown (HSG) film over a conductive surface; subjecting said HSG film to a remote plasma nitridation treatment; forming a metal oxide film over said HSG film; thermally annealing said metal oxide film in the presence of an oxygen containing ambient; and, depositing an electrode film by a low temperature CVD process carried out at a temperature of at most about 580 degrees Centigrade.
In another embodiment according to the present invention, a method is provided for reducing a thermal budget in a semiconductor manufacturing process including the steps of: forming a hemispherical surface crown (HSG) film over a conductive surface; subjecting said HSG film to a remote plasma nitridation treatment; forming a metal oxide film over said HSG film; subjecting said metal oxide film to a plasma oxidation treatment in the presence of an oxygen containing ambient; and, depositing an electrode film by a process selected from the group consisting of atomic layer deposition, and physical vapor deposition.
Additional embodiments are presented according to the present invention where a thermal annealing and plasma oxidation step in the presence of at least N
2
O may be carried alternatively or additively to one another.
Yet additional embodiments include specific temperatures and materials for carrying out the steps according to the present invention.


REFERENCES:
patent: 6207497 (2001-03-01), Huang et al.
patent: 6337289 (2002-01-01), Narwankar et al.
patent: 6376299 (2002-04-01), Joo et al.
patent: 6458645 (2002-10-01), DeBoer et al.
patent: 2001/0024387 (2001-09-01), Raaijmakers et al.

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