Method of producing low-resistance diffused regions in IC MOS se

Details Method of producing low-resistance diffused regions in IC MOS se Method of producing low-resistance diffused regions in IC MOS se

1980-06-09

1982-11-02

Rutledge, L. Dewayne

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29590, 29591, 148174, 148188, 357 23, 357 59, 357 67, 357 71, 427 88, 427 91, H01L 21225, H01L 21283

Patent

active

043566227

ABSTRACT:
Low-resistance diffused regions useful as current-supply paths in IC MOS semiconductor circuits in silicon-gate technology are produced by forming a metal silicide on a doped polysilicon layer positioned on a substrate, applying a SiO.sub.2 layer over the silicide layer, structuring the resultant SiO.sub.2 -silicide-polysilicon triple layer in such a manner that areas of the substrate where the low resistance diffused regions are desired remain covered, thereafter executing gate oxidation and completing fabrication of the desired circuit.

REFERENCES:
patent: 3574010 (1971-04-01), Brown
patent: 3600235 (1971-08-01), Okumura
patent: 3667008 (1972-05-01), Katnack
patent: 3887993 (1975-06-01), Okada et al.
patent: 3918149 (1975-11-01), Roberts
patent: 3942241 (1976-03-01), Harigaya et al.
patent: 4063901 (1977-12-01), Shiba
patent: 4069067 (1978-01-01), Ichinobe
patent: 4151631 (1979-05-01), Klein

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