Method of producing integrated semiconductor structures comprisi

Details Method of producing integrated semiconductor structures comprisi Method of producing integrated semiconductor structures comprisi

1989-03-21

1990-12-25

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437225, 437229, 437235, 148DIG51, 148DIG137, 156643, 156646, 156657, 1566591, 156660, 1566611, H01L 2100, H01L 2102, H01L 21306, H01L 21308

Patent

active

049803174

ABSTRACT:
Disclosed is a method of producing an integrated semiconductor structure, comprising components with dimensions in the submicron range, wherein a three-layer resist system is used to produce a polymer or resist mask. The polymer or resist mask thus produced is used to etch a layer of polysilicon on the semiconductor substrate. The method is characterized in that the pattern, produced conventionally in the top layer of the three-layer resist and including an angle < about 90.degree., is transferred by RIE, using CF.sub.4, to the center layer of plasma nitride and by RIE, using oxygen, to the bottom resist or polymer layer. In a prior art method, this was followed by lateral etching in oxygen to reduce the dimensions of the mask by a desired amount. The improved method of the invention provides for the plasma nitride mask to be removed first, using, if necessary a facetting step in oxygen to increase the positive angle in the mask structure, and then for the latter structure to be laterally etched in oxygen to reduce its dimensions by the desired amount. As the angle in the mask is < about 90.degree., the parameters for lateral etching may be chosen such that the etch process is largely anisotropic and, thus, accurately and readily determinable. As a result, the absolute amount of lateral etching may be accurately adjusted during the etch period. As shading plasma nitride is removed before lateral etching, the influence of neighboring structures on lateral etching is largely reduced. The mask thus produced is used to etch in the polysilicon layer structures whose angles ensure a good definition of the spacers to be produced in the subsequent process steps and of ion implantation, which both determine the effective channel length of field-effect transistors.

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