Method of producing enhancement mode and depletion mode FETs

Details Method of producing enhancement mode and depletion mode FETs Method of producing enhancement mode and depletion mode FETs

1985-04-29

1986-10-07

Ozaki, George T.

Metal working

Method of mechanical manufacture

Assembling or joining

29577C, 29578, 29580, 148175, 148187, 156646, H01L 21205

Patent

active

046151028

ABSTRACT:
A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate, a channel layer, an electron-supply layer, a third layer, a first etching-stoppable layer, a fifth layer, and a second etching-stoppable layer, which layers are formed in sequence on the substrate. An etching process for forming grooves of gate electrodes of the FETs comprises a first etching treatment removing the first etching-stoppable layer portion in the E-mode FET region and the second etching-stoppable layer portion in the D-mode FET region, and a second etching treatment removing the third layer portion in the E-mode FET region and the fifth layer portion and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CCl.sub.2 F.sub.2 etchant gas is adopted, since GaAs can be thereby rapidly etched as compared with AlGaAs used for the etching-stoppable layer material.

REFERENCES:
patent: 4371968 (1983-02-01), Trussell et al.
patent: 4523961 (1985-06-01), Hartman et al.
patent: 4545109 (1985-10-01), Reichert
patent: 4575924 (1986-03-01), Reed et al.
Solid State Devices 1982, ESSDERC-SSSDT Meeting in Munich, 13th-16th Sep. 1982, pp. 25-50, Physik-Verlag, Weinheim D. E.; M. Abe et al., "Advanced Device Technology for High Speed GaAs VLSI".
Japanese Journal of Applied Physics, vol. 20, No. 11, Nov. 1981, pp. L847-L850, Tokyo, JP, K. Hikosaka et al., "Selective Dry Etching of AlGaAs-GaAs Heterojunction".

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