Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Patent
1996-03-05
1997-08-12
Nieblinh, John
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
257786, 29827, 438124, H01L 2160
Patent
active
056565500
ABSTRACT:
This invention relates to a semiconductor device in which a plurality of outer terminals are arranged in a lattice formation on a flat surface. The semiconductor device has a semiconductor chip, a lead member having a lead portion and an outer connecting terminal connected integrally to the lead portion, the lead portion electrically connected to the semiconductor chip, the lead portion extending outwardly from the semiconductor chip, the outer connecting terminal extending downwardly from the lead portion, a sealing resin sealing the semiconductor chip and the lead portion, a bottom face of the semiconductor chip and a bottom face of the lead portion being exposed from the sealing resin, and an insulating member covering the bottom face of the semiconductor chip and the bottom face of the lead portion. Also, the semiconductor device has a semiconductor chip having a predetermined number of electrode pads, a predetermined number of leads electrically connected to the electrode pads, each of the leads having a projecting terminal portion formed by bending the lead, and a resin portion sealing the semiconductor chip and the leads, wherein the terminal portions are exposed from one face of the resin portion.
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patent: 5475236 (1995-12-01), Yoshizaki
patent: 5508556 (1996-04-01), Lin
Nomoto Ryuji
Onodera Masanori
Orimo Seiichi
Sakoda Hideharu
Tsuji Kazuto
Fujitsu Limited
Nieblinh John
Turner Kevin
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