Method of producing a semiconductor layer on a substrate

Details Method of producing a semiconductor layer on a substrate Method of producing a semiconductor layer on a substrate

2001-12-19

2003-08-05

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

C438S458000, C438S409000

Reexamination Certificate

active

06602760

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to a method of realising a bond between a substrate, preferably a Si-substrate and a thin semiconductor layer, such as a Ge layer. The present invention is equally related to products resulting from such a method.
STATE OF THE ART
Ge-substrates are often used as a substrate for the growth of active III-V devices (e.g. multijunction monolithic cascade solar cells or LED's). However, a Ge-substrate is much more expensive than a Si-substrate, and more importantly, Si has a much higher strength than Ge (by a factor of 2) and lower density.
Therefore, the realisation of a Ge-layer on a Si-substrate has gained a large importance for the production of opto-electronic applications.
The epitaxial growth of GaAs layers on Ge-substrates is known to give good results due to the good lattice match between these two materials. When it comes to growing Ge (or GaAs) layers on Si, however, problems occur due to a lattice mismatch of over 4% for both Ge and GaAs, compared to Si.
First of all, techniques are documented in the literature, to combine Si and GaAs.
Document U.S. Pat. No. 4,959,308 describes a method of forming a GaAs layer on Si wherein a defect annihilating grid is formed on the Si substrate prior to the epitaxy of GaAs, in order to reduce the effects of lattice mismatch.
Known methods of producing GaAs layers on Si-substrates however do not allow to produce GaAs layers with defect densities lower than 10
5
-10
6
cm
−2
, which is still one order of magnitude too high to realise devices with a good energy conversion efficiency.
Document U.S. Pat. No. 4,806,996 describes a device wherein an epitaxial layer, such as Ge or GaAs is formed on a single crystal substrate, such as a Si substrate, and wherein the surface of said substrate is suitably patterned in order to reduce lattice mismatch effects. The process required for producing said device is however complex and comprises many process steps.
Alternatively, methods have been reported of realising a graded layer of SiGe, which is rich in Si at the Si substrate and gradually becomes pure Ge near the top of the layer.
By the Ge-grading, the number of threading dislocations is kept low, because the misfit dislocations bend sidewards. The grading, which is optimally in the order of a change of 10% Ge per &mgr;m, is realised by adapting the growth parameters during growth. Growth of GaAs-layers on such graded buffer layers of Ge on Si has been realised and photoluminescence measurements give evidence of the good quality of the GaAs epitaxial layer.
A method of growing such a GexSi1-x layer on a Si substrate by molecular beam epitaxy is described in document U.S. Pat. No. 4,529,455.
A drawback of this kind of graded layer is the cost of the process used, which is comparable to the cost of the Ge-substrate. This is a consequence of the growth procedure used.
AIMS OF THE INVENTION
The method according to the present invention aims to provide a stable bond preferably between a semiconductor substrate and a semiconductor layer, without applying intermediate layers, patterning of the substrate or epitaxy of a graded layer.
SUMMARY OF THE INVENTION
The present invention is related to a method of producing a semiconductor layer onto a semiconductor substrate, comprising the steps of:
Providing a first semiconductor substrate,
Providing a second semiconductor substrate,
Producing a porous layer on top of said first semiconductor substrate, said layer having a porosity profile,
Producing a porous layer on top of said second semiconductor substrate, said layer having a porosity profile,
Bringing said porous layer of said second substrate into contact with said porous layer of said first substrate, so as to form a bond between said two substrates,
Performing a thermal annealing step,
Lifting off said second substrate, leaving a layer of said second substrate's semiconductor material attached to said first substrate.
Said porosity profile of said second substrate may be formed by a first layer of high porosity adjacent to said second substrate's surface, followed by a second layer of lower porosity and a third layer of high porosity.
Said porosity profile of said first substrate may be formed by a first layer of high porosity adjacent to said first substrate's surface, followed by a second layer of lower porosity.
According to a preferred embodiment, a layer of the material of said second substrate is formed on top of said first substrate, said layer comprising a number of voids.
Said first substrate may be a Si-substrate and said second substrate a Ge-substrate. Said first substrate may be a Si substrate and said second substrate a GaAs substrate. Both said first and said second substrates may be Si substrates.
Said forming of porous layers may be done by an anodization step.
The method according to the invention may comprise the steps of:
forming a porous layer on said second substrate through anodization in a solution of HF and acetic acid,
bringing said first substrate into contact with said second substrate while said second substrate is still in the solution used to perform said anodization.
According to another embodiment, the method according to the invention comprises the steps of:
forming a porous layer on said second substrate through anodization in a solution of HF and acetic acid,
removing said second substrate from said solution,
bringing said first substrate into contact with said second substrate.
The present invention is equally related to a semiconductor device, produced with the method of the invention. Said device may be an opto-electronic device.


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Bilyalov, R.R., et al., “Thin Silicon Films for Solar Cells Based on Porous Silicon”, 16thEuropean Photovoltaic Solar Energy Conference, pp. 1536-1540, (May 1-5, 2000).

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