Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-08-03
2001-04-10
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S106000
Reexamination Certificate
active
06214639
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to producing semiconductor devices and, more particularly, to a technology useful at the time of separating a semiconductor wafer, after completion of a wafer process, into individual chips and installing the chips into respective packages.
2. Description of the Related Art
Conventionally, in installing the chips of semiconductor devices into packages in an assembling process, an automatic chip bonder is used to ensure mass-production capability and working efficiency.
Such a automatic chip bonder attaches chips, separated from a semiconductor wafer after completion of a wafer process, by a scribing process and a separation process, to the respective packages by die bonding, and bonds wires of gold, aluminum or the like between each chip and its associated package by wire bonding. For this process, the automatic chip bonder must precisely identify the position of each of the chips aligned on a plane, through pattern recognition of the outline of each chip and the positions of the electrodes. Accurate recognition of the position of each chip requires the regular alignment of the individual chips.
In other words, if the chips are not in a regular alignment, the automatic chip bonder cannot accurately recognize the chip position. This results in an installation of the individual chips in the respective packages at lower efficiency and lower mass-production.
One conventional way of coping with this problem is to form a thin insulating film or the like on the top surface of a semiconductor wafer in such a way as to link between chips prior to the use of an automatic chip bonder, to use the thin film to link the chips, to adhere the thin film to an extension tape while keeping the aligned state of the chips, then to cut the thin film to separate the individual chips, and to stretch the extension tape to widen the interval between the chips. The reason for using the extension tape is that a sufficient space between the chips facilitates the work of holding each chip with a pincette, a collet or the like in the assembling process.
In the following description, the term “chip” strictly means an individual semiconductor device separated from a semiconductor wafer, and a corresponding portion of a semiconductor wafer before separation is referred to as a “semiconductor-device forming portion” and will also be conveniently referred to as a “chip” unless confusion occurs.
Also, in the following description, the “top surface” of a semiconductor substrate (or wafer) specifically indicates the surface on which semiconductor devices are formed, unless otherwise particularly defined, and the surface of the opposite side is referred to as the “back surface” of a semiconductor substrate (or wafer).
Since, in the prior art as mentioned above, a thin insulating film or the like is used where individual chips (semiconductor-device forming portions) are to be linked, the thin film may be sheared if more stress than required is applied to the thin film during a process of treating the back surface of the semiconductor wafer (e.g., adjustment of the thickness of the semiconductor substrate, formation of electrode regions, and the like) or in a process up to the separation of the chips. This structure does not therefore have a sufficient strength.
Also, if the thin film is sheared before the intended chip separation, the individual chips are fed to an automatic chip bonder, and are improperly aligned. This results in a lower working efficiency in the assembling process and in a lower mass-production.
Further, this prior art needs space for forming a thin film for linkage of chips at the periphery of the top surface of each chip and, thus, requires a larger chip size accordingly. In other words, this prior art has such a disadvantage that the number of effective chips obtainable from a single semiconductor wafer becomes relatively smaller. This eventually leads to a lower mass-production, and thus improvement is needed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of producing a semiconductor device, which can ensure a higher working efficiency in the assembling process and improved mass-production capability.
According to the present invention, there is provided a method of producing a semiconductor device, which comprises a first step of forming separation grooves in scribing regions defined at boundary portions between a plurality of semiconductor-device forming portions formed on a top surface of a semiconductor substrate; a second step of defining portions of the scribing regions in the semiconductor substrate as substrate connecting portions; and a third step of cutting off the substrate connecting portions along the separation grooves, to thereby separate the plurality of semiconductor-device forming portions into chips.
According to the semiconductor device producing method of this invention, a portion (substrate connecting portion) of a semiconductor substrate, which is relatively strong, is used where individual chips (semiconductor-device forming portions) are to be linked, and thus it is strong enough as a chip linking member. It is therefore possible to firmly link the individual chips until chip separation and to feed the individual chips to an automatic chip bonder, while being property aligned. This allows the automatic chip bonder to precisely identify each chip position, to thereby ensure an efficient installment of the chips into packages. Namely, it is possible to improve both the working efficiency in the assembling process and mass-production.
Further, unlike the prior art, since the present invention requires no space for forming a thin film for linkage of chips on the top surface of each chip, the chip size can accordingly be made smaller, and eventually the number of effective chips obtainable from a single semiconductor wafer can be increased. This contributes to a further improvement in the mass production efficiency.
Since the substrate connecting portion which is cut off at the time of chip separation is formed by a portion of the semiconductor substrate which is relatively strong, it does not appear easy to cut off the substrate connecting portion. Since the separation groove is formed in the scribing region defined in the portion corresponding to the substrate connecting portion, however, the substrate connecting portion can easily be cut off without applying large stress to the semiconductor substrate by, for example, merely applying slight force to the substrate connecting portion along the separation groove at the time of chip separation.
REFERENCES:
patent: 4209355 (1980-06-01), Burns
patent: 5434094 (1995-07-01), Kobiki et al.
patent: 5919713 (1999-07-01), Ishii et al.
patent: 57-49252 (1982-03-01), None
patent: 4-116950 (1992-04-01), None
Emori Masaomi
Hiratsuka Kenichi
Ishii Masanori
Kawakubo Hiroshi
Nunokawa Mitsuji
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Nelms David
Nhu David
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