Method of producing a large-scale integrated MOS field-effect tr

Details Method of producing a large-scale integrated MOS field-effect tr Method of producing a large-scale integrated MOS field-effect tr

1987-04-21

1989-02-21

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 58, 437 34, 437 28, 437239, 148DIG118, H01L 2170, H01L 21316

Patent

active

048065005

ABSTRACT:
A method of producing a large-scale integrated MOS field effect transistor circuit which includes forming p and n-doped troughs, respectively, in a silicon substrate to accommodate respective n and p-channel transistors, introducing appropriate dopant atoms into the troughs by repeated ion implantations to adjust various transistor cutoff voltages, and masking the various ion implantations with photo resist structures and/or with silicon oxide and silicon nitride structures, respectively, and which includes forming source/drain and gate areas as well as forming intermediate and insulation oxide and a strip conductor plane in accordance with conventional MOS technology methods includes the steps of: applying a total-area oxide film having a first film thickness (d1.sub.G); removing the oxide in a given area (II) associated with an n-channel transistor; and applying another, total-area oxide film in such a manner that, in anothedr area (III) associated with another n-channel transistor, the oxide film attains a final thickness (d.sub.G) which is greater than the first film thickness (d1.sub.G), may be followed by the steps of: applying a mask to a gate oxide with a window in a given area (II); implanting with first dopant atoms to produce n.sup.+ source/drain areas of a first n-channel transistor, dosage and implantation energy thereof being adapted to a second film thickness (d3.sub.G) of the gate oxide; applying a mask to a gate oxide with a window in another area (III); implanting with second dopant atoms to produce an n+ source/drain area of a second n-channel transistor, the dosage and implantation energy thereof being adapted to a final thickness (d.sub.G); removing that part of the gate oxide surface which is contaminated; and driving the implanted dopant atoms into the given area (II) and the other area (III).

REFERENCES:
patent: 4110899 (1978-10-01), Nagasawa et al.
patent: 4471373 (1984-10-01), Shimizu et al.
Ghandhi, VLSI Fabrication Principles, John Wiley and Sons, 1983.

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