Method of producing a fully planarized concave transistor

Details Method of producing a fully planarized concave transistor Method of producing a fully planarized concave transistor

1996-11-22

1997-10-14

Trinh, Michael

Fishing, trapping, and vermin destroying

437 40RG, 437 44, 437203, 437 41RLD, H01L 218232

Patent

active

056772106

ABSTRACT:
A fully planarized concave transistor is produced having a structure, wherein a lightly doped drain(LDD) region and a source/drain region are formed and accumulated on a semiconductor substrate in a predetermined pattern, a thick insulating layer is formed on the surface and the sidewall of the source/drain, a gate formed between the source and drain, with a gate insulating layer is formed between the source and the gate, and between the drain and the gate to insulate therebetween.

REFERENCES:
patent: 5108937 (1992-04-01), Tsai et al.
patent: 5164325 (1992-11-01), Cogan et al.
patent: 5270257 (1993-12-01), Shin
patent: 5382534 (1995-01-01), Sheu et al.
S. M. Sze; "VLSI Technology", pp. 131-142; 1983.

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