Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates – Thinning of semiconductor substrate
Reexamination Certificate
2001-03-13
2004-04-06
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
Thinning of semiconductor substrate
C438S455000
Reexamination Certificate
active
06716722
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of improving flatness of a base wafer and suppressing generation of particles in a process for producing the bonded wafer having SOI layer or a silicon active layer.
BACKGROUND ART
Recently, public attention has been especially drawn to so called SOI (silicon on insulator) structure having a silicon active layer on a silicon oxide film with electrical insulation property, since it has characteristics of high speed of device, low electricity consumption, high breakdown voltage, high resistance to environment. As a typical method for producing such a SOI wafer having SOI structure, there has been the bonding method.
The bonding method is a technique wherein two silicon wafers are bonded via a silicon oxide film. For example, as shown in Japanese patent publication No. 5-46086, an oxide film is formed on at least one of the wafers, and closely contacted each other without interposing impurities at a contacted surface, and subjected to heat treatment at a temperature of 200 to 1200° C. in order to increasing bonding strength. The bonded wafer whose bonding strength is increased by the heat treatment can be then subjected to a grinding and polishing process. Accordingly, the wafer on which a device is fabricated (bond wafer) can be subjected to grinding and polishing process reduce its thickness as desired, and thereby a SOI layer on which a device is formed can be formed.
The bonded SOI wafer produced as above is excellent in crystallinity of the SOI layer, and has an advantage of high reliability of buried oxide layer just under the SOI layer. However, the thickness thereof is reduced by grinding and polishing, which process takes long time for reducing thickness. Moreover, material is wasteful Furthermore, film thickness uniformity is generally in the range of ±0.5 &mgr;m of target thickness, which has been the largest technical subject of technology. As a method of reducing a film thickness for solving a problem of film thickness uniformity in the bonding method, there have been developed a so-called PACE (Plasma Assisted Chemical Etching) method disclosed in Japanese Patent publication No. 2565617, and a hydrogen ion delamination method (occasionally called smart-cut method) disclosed in Japanese Patent Application Laid-open (Kokai) No.5-211128.
PACE method is a method for making film thickness of SOI layer uniform according to vapor phase etching wherein SOI wafer produced by the bonding method (thickness of the SOI layer is several &mgr;m±0.5 &mgr;m) is prepared, distribution of thickness of the SOI layer to be uniform is measured to make a map of thickness distribution, thick part is removed by vapor phase etching (plasma etching) with control of value according to the map, so that the SOI layer with very thin and uniform thickness can be formed.
The hydrogen ion delamination method is a method wherein an oxide film is formed on at least one of two silicon wafers; at least one of hydrogen ions and rare gas ions is implanted into the upper surface of one of the wafers in order to form a fine bubble layer (enclosed layer) within the silicon wafer; the ion-implanted surface is brought into close contact with the other silicon wafer via the oxide film; heat treatment (delaminating heat treatment) is then performed to delaminate a portion of one of the wafers using the fine bubble layer as a cleavage plane (delaminating plane), in order to form a thin film; and heat treatment (bonding heat treatment) is further performed to firmly bond them, to provide an SOI wafer. Although the surface of the SOI wafer produced as above (a delaminated surface) is a relatively good mirror-like surface, it is subjected to a mirror polishing process, called “touch polishing”, wherein a stock removal is very small, in order to provide SOI wafer having surface roughness equivalent to the general mirror polished wafer.
According to this method, an SOI wafer whose SOI layer has a very high thickness uniformity can be obtained relatively easily. Furthermore, the delaminated wafer can be reused, namely there is also an advantage that the material can be efficiently used.
Moreover, silicon wafers can be directly bonded without the oxide film, and it is possible to use the method not only for bonding silicon wafers each other, but also for bonding the ion-implanted silicon wafer to insulator wafer having different thermal expansion coefficient such as quartz, silicon carbide, alumina or the like.
As a result of development of these techniques for reducing film thickness, it has become possible to produce a bonded SOI wafer having SOI layer of very thin thickness of 0.1±0.01 &mgr;m and excellent thickness distribution. As a result, use of a bonded SOI wafer has been significantly broaden, and therefore it is expected to be applied to the most advanced device having very fine pattern or a special structure. Furthermore, a similar bonding method can also be applied to a wafer produced by directly bonding the silicon wafers without an oxide film.
In the bonding method, if surface roughness of two silicon wafers to be bonded each other is a mirror polished surface at general product grade, it is possible to produce the bonded wafer without generating bonding failure such as void or the like at bonding interface. Therefore, as a wafer to be used, mirror polished wafer (hereinafter occasionally referred to as PW) having general product grade has been used.
A method for producing PW comprises, as conventionally known, steps of slicing a silicon ingot, and a step of subjecting the resulting silicon wafer to, at least, chamfering, lapping, acid etching, mirror polishing of one surface and cleaning or the like. Depending on the purpose, the order of these steps can be partly changed, some of these steps can be repeated, or other steps such as a heat treatment step, a grinding step or the like can be added or changed thereto. Among these steps, the acid etching step is conducted in order to remove a surface degraded layer due to working of the surface introduced during mechanical machining such as slicing, chamfering, lapping or the like. It is conducted, for example, by etching with an acid mixture comprising hydrofluoric acid, nitric acid, acetic acid and water with an etching amount of several &mgr;m to several tens &mgr;m from the surface. Regarding this step, the following problems have been pointed out in the step.
1) Flatness of the lapped wafer having a deviation of thickness as expressed by TTV [Total Thickness Variation] (&mgr;m), LTV
max
[Local Thickness Variation] (&mgr;m) or the like is degraded more when the etching amount is more.
2) Waviness having a cycle in mm order or unevenness called peal is generated on the etched surface.
3) Harmful NOx is generated by etching.
Taking these problems into consideration, alkali etching is sometimes used.
Advantages and disadvantages of the alkali etching are explained below.
Advantages are as follows:
a) Flatness after lapping is maintained even after etching.
b) Generation of harmful gas is suppressed.
Disadvantages are as follows:
a) Pits having a depth of several &mgr;m and a size of several &mgr;m to several tens &mgr;m are present locally on the etched surface. Therefore, if impurities get into the pits, they may cause generation of particles and contamination in the following steps.
b) Since deep pits are present, and surface roughness (Ra) is increased, it is necessary to increase stock removal in the following mirror polishing step (mechanochemical polishing).
c) The shape of unevenness of the surface after alkali etching is sharp compared with acid etching treatment. Therefore, such unevenness itself may cause generation of particles.
Meanwhile, the most serious problem in the bonding method before the above-mentioned PACE method and the hydrogen ion delamination method have been developed was uniformity of the thickness of the SOI layer. As described above, since the bonding method comprises bonding a bond wafer to be made thin and a base wafer for suppo
Furihata Jun-ichiro
Mitani Kiyoshi
Lattin Christopher
Niebling John F.
Oliff & Berridg,e PLC
Shin-Etsu Handotai & Co., Ltd.
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