Etching a substrate: processes – Etching and coating occur in the same processing chamber
Reexamination Certificate
2000-03-01
2003-08-26
Beck, Shrive P. (Department: 1763)
Etching a substrate: processes
Etching and coating occur in the same processing chamber
C216S063000, C134S022100, C134S026000, C438S905000, C438S911000
Reexamination Certificate
active
06610211
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods of processing internal surfaces of a chemical vapor deposition reactor.
BACKGROUND OF THE INVENTION
Chemical vapor deposition reactors, with or without plasma, are commonly used in semiconductor processing to deposit layers over semiconductor wafers. This invention grew out of concerns associated with cleaning internal surfaces of such reactors, particularly after depositing Ta
2
O
5
and other high K capacitor dielectric layers onto wafers received within the reactors. In the context of this document, “high K” means materials having a dielectric constant of at least 20.
Particularly, as DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs will be on the order of 0.25 micron, and conventional dielectrics such as SiO
2
and Si
3
N
4
might not be suitable because of small dielectric constants.
Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO
2
equivalent thickness.
Insulating inorganic metal oxide materials, such as ferroelectric materials or perovskite material or pentoxides such as tantalum pentoxide, have high dielectric constants (K) and low leakage current which make them attractive as cell dielectric materials for high density DRAMs and non-volatile memories. Perovskite material and other ferroelectric materials exhibit a number of unique and interesting properties. One such property of a ferroelectric material is that it possesses a spontaneous polarization that can be reversed by an applied electric field. Specifically, these materials have a characteristic temperature, commonly referred to as the transition temperature, at which the material makes a structural phase change from a polar phase (ferroelectric) to a non-polar phase, typically called the paraelectric phase.
Chemical vapor deposition techniques commonly used in forming these high K and other oxygen containing dielectrics utilize organic precursors, such as metal organic and organometallic precursors. For example,
FIG. 1
depicts a chemical vapor deposition reactor
10
having a circular plate or wafer platen
12
upon which a plurality of semiconductor wafers
14
is received. Wafer platen
12
is typically comprised of SiC. Reactor
10
includes one or more gas inlets
16
and one or more gas outlets
18
. Precursor gases would be injected through inlet(s)
16
for achieving deposition of a desired layer atop wafers
14
. For example where the deposition is for a high K Ta
2
O
5
layer, low pressure chemical vapor deposition can be conducted utilizing Ta(C
3
H
5
)
5
, O
2
and N
2
as precursor gases. Example flow rates are 120 sccm; 2-5 slm; and 2-5 slm, respectively. An example temperature is 410° C., with an example pressure being from 200 to 400 mTorr. Unfortunately, deposition in such systems also results in deposition not only over wafers
14
, but also over SiC substrate
12
and other internal wafer surfaces. Typically at least monthly, the chamber needs to be cleaned to remove deposited dielectric material from the SiC platen
12
and other reactor surfaces.
One present technique for doing so includes an HF vapor etch at 400° C. for four hours. This etch is largely selective to etch Ta
2
O
5
selectively relative to the typical SiC material of wafer platen
12
. Such can, however, leave a black carbon residue atop internal reactor surfaces, typically emanating from the organic precursor used to deposit the Ta
2
O
5
, and which is not etched by the HF. The present conventional way for ridding the reactor surfaces of this organic material is by utilizing an O
2
burn, for example at 800° C.-850° C. at from 1 Torr to 10 Torr. Such effectively removes the carbon, and provides a clean deposition tool for subsequent processing of wafers.
Unfortunately, there are drawbacks associated with such processing. A first drawback is that the HF etch rate of the Ta
2
O
5
material over the SiC substrate
12
is slower than desired. A second drawback concerns the subsequent extreme high temperature processing at 800+° C. for ridding the tool of carbon. These large deposition tools apparently can take as much as another week after cleaning to cool down and achieve stabilized temperatures during deposition of the material over the wafers. During this time period, deposition rate is impacted by as much as 25% of the desired thickness of the films being deposited, thus creating unpredictability and process complexity.
It would be desirable to at least partially overcome some of these problems.
SUMMARY OF THE INVENTION
The invention encompasses methods of processing internal surfaces of a chemical vapor deposition reactor. In one implementation, material is deposited over internal surfaces of a chemical vapor deposition reactor while processing semiconductor substrates therein. The deposited material is treated with atomic oxygen. After the treating, at least some of the deposited material is etched from the reactor internal surfaces. In one embodiment, first etching is conducted of some of the deposited material from the reactor internal surfaces. After the first etching, remaining deposited material is treated with atomic oxygen. After the treating, second etching is conducted of at least some of the remaining deposited material from the reactor internal surfaces. In one embodiment, the deposited material is first treated with atomic oxygen. After the first treating, first etching is conducted of some of the deposited material from the reactor internal surfaces. After the first etching, second treating is conducted of remaining deposited material with atomic oxygen. After the second treating, second etching is conducted of at least some of the remaining deposited material from the reactor internal surfaces.
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Al-Shareef Husam N.
DeBoer Scott Jeffrey
Gealy F. Daniel
Beck Shrive P.
Micro)n Technology, Inc.
Olsen Allan
Wells St. John P.S.
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