Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-03-01
2011-03-01
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S118000, C716S119000
Reexamination Certificate
active
07900177
ABSTRACT:
A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern density and the value of the length of the periphery of the wiring pattern and the dummy pattern in the wiring region falls within specified ranges in the wiring region.
REFERENCES:
patent: 7062732 (2006-06-01), Ito et al.
patent: 7171645 (2007-01-01), Ito et al.
patent: 2004/0102034 (2004-05-01), Ito et al.
patent: 2004/0139412 (2004-07-01), Ito et al.
patent: 2000-277615 (2000-10-01), None
patent: 2002-198435 (2002-07-01), None
Scagnelli et al.,“Pattern Density Methodology Using IBM Foundry Technologies”, May 2007, 57thElectronic Components and Technology Conference, Proceedings pp. 1300-1307.
Lin Sun J
McGinn IP Law Group PLLC
Renesas Electronics Corporation
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