Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
1999-11-04
2002-05-21
Le, Vu A. (Department: 2824)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S118000, C438S464000
Reexamination Certificate
active
06391679
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a method of processing a substantially wafer-shaped product in semiconductor technology, which product is designed for the formation of a number of electronic circuit bodies over at least a first of its main surfaces, which circuit bodies are to be mechanically separated substantially perpendicularly to the first main surface, and which product has a second main surface lying opposite the first main surface.
European patent application 0 800 205 discloses a method of separating electronic elements joined together in one body, wherein the side of the body facing away from the electronic elements is made thinner, the electronic elements are separated from one another, and electrical parameters of the electronic elements are tested after thinning of the body. Handling of the body is said to be improved in that before the thinning process an electrically non-conductive auxiliary layer is provided on the side of the body which comprises the electronic elements, in which auxiliary layer contact openings are formed above the electronic elements such that they each expose the contact(s) of the relevant electronic element. After the electrical parameters of the electronic elements have been tested, the electronic elements which are to be further used are selected and supplied to a device for further processing. The electronic elements still remain interconnected by means of bridges in the auxiliary layer until that moment. These bridges of the auxiliary layer are to be removed in said device, so that the electronic elements are also mechanically separated from one another. The auxiliary layer remains on the side of the body which comprises the electronic elements. The result of this is that the electronic elements will have a greater total constructional height than would be the case without said auxiliary layer, unless further measures are taken. In addition, the auxiliary layer requires additional, specialized processing steps, i.e. the manufacture of the contact openings and the bridges as well as severing of the latter. Moreover, it is necessary in this process to separate the body supporting the electronic elements in a direction starting from the side facing away from these elements for the purpose of separating the individual elements. This separation “from below”, which is to be effected, for example, by etching, involves a considerable cost in particular for small structures of the electronic elements in order to safeguard a sufficiently accurate alignment for positioning the incisions. If a sawing process is used instead of etching, the additional disadvantage would arise that the surface of the body facing away from the sawing blade often tends to crumble during the sawing process, and that in this case the surface threatened by the crumbling process is the one which carries the electronic elements. This would increase the reject rate.
A method is known from the English abstract of publication JP 61-8938 (A) wherein a wafer with semiconductor elements is glued to a thermoelastic adhesive tape. The elements are separated from one another in that the tape is stretched out, are then electrically tested, and are removed from the tape. After the separation, however, the electrical measurements can only be carried out for individual elements, in particular in the case of very fine conductor structures on the semiconductor elements, since the exact geometric alignment of the elements in relation to one another is no longer guaranteed owing to the stretching of the tape. This means that multiple tests, i.e. simultaneous electrical measurements of a number of elements on a wafer, are no longer possible, or only with devices which require thorough and complicated alignment procedures.
A method is known from the English abstract of publication JP 5-341000 (A) wherein integrated circuits are individually taken up and subjected to an individual test after a wafer has been split up. Then the integrated circuits are laid on a new carrier in given positions and subjected thereon to a further, final test. Here a very expensive alignment step is to be carried out for arranging the integrated circuits on the further carrier, quite apart from the testing step which is individually carried out.
U.S. Pat. No. 5,456,404 furthermore discloses a similar process for testing semiconductor circuits. In this process, a special test housing is utilized in which the circuits are individually contacted and tested. It is to be achieved by means of a special construction of the contacts of the test housing that an increase in the pressure applied to the electronic circuit in the test housing fixes the circuit permanently in the housing in the case of a positive result of the electrical test, so that the test housing can be utilized also as a permanent housing for the integrated circuit. This, however, also requires a considerable cost and effort in the testing process and for the housing.
SUMMARY OF THE INVENTION
The invention has for its object to provide a method of the kind mentioned in the opening paragraph such that an inexpensive manufacture of semiconductor technology products can be combined with the simplest possible handling while at the same time complying with stricter requirements which are imposed in particular by the ever-increasing miniaturization of the conductor structures of the electronic circuit bodies formed on these products.
According to the invention, this object is achieved in a method as defined in the preamble of claim
1
in that, for carrying out processing steps on one of the main surfaces of the product, a layer of adhesive material is provided in a planar manner on the opposite main surface of the product, on which layer a carrier element of at least substantially stable shape is provided so as to achieve a planar connection to said opposite main surface of the product.
Such a semiconductor technology product within the scope of the teachings of the present invention is preferably a wafer of semiconductor material, for example of doped silicon. Alternatively, however, other materials may also be used, both elementary materials and compounds, metalloid or non-metallic. The word “wafer” is understood to mean an at least substantially cylindrical body with a small height in relation to its transverse dimensions hereinafter. The word “cylindrical” is understood to relate here to a body whose diameter measured perpendicularly to its longitudinal axis, its cylinder axis, has an at least substantially unchanged shape and dimension over its entire length along said cylinder axis. Whereas the diameter dimensions of the cylindrical body are measured perpendicularly to the cylinder axis, the height of the cylindrical body is measured parallel to the cylinder axis. The main surfaces of such a wafer are formed by the surfaces of the cylindrical body which face outwards in the direction of the cylinder axis. These main surfaces extend at least substantially parallel to one another in a wafer of the kind described. They then have a contour which corresponds at least substantially to a cross-sectional surface extending at right angles to the cylinder axis through the cylindrical body. Preferably, wafers with at least substantially circular main surfaces are used in semiconductor technology, wherein a number of electronic circuit bodies are formed on the first main surface, also called upper surface, while on the second main surface opposed to the first main surface a passivating or conductive layer is usually provided. This second main surface is then denoted the lower surface of the wafer.
The application of a semiconductor technology product as described on the carrier element in accordance with the invention renders it possible in a simple manner to subject said product to processing steps in manufacturing devices also if the product itself should not be suitable for the relevant processing steps and/or manufacturing devices on account of its dimensions or structures. This is true in particular for products with geometrically very smal
Anker Joachim
Burmeister Frank
Dichte Olaf
Biren Steven R.
Le Vu A.
Smith Brad
U.S. Philips Corporation
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