Method of processing a semiconductor device

Details Method of processing a semiconductor device Method of processing a semiconductor device

2000-08-22

2001-12-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C257S215000

Reexamination Certificate

active

06329219

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method of processing a semiconductor device and in particular to a method for processing a semiconductor device to provide an integrated circuit that includes a functional resistor. Although some aspects of this invention may be applied to semiconductor devices other than charge-coupled devices (CCDs), certain aspects of the invention are particularly useful when applied to a CCD and therefore the invention will be described in the context of a CCD. Further, it will be understood by those skilled in the art that there are many different types of CCDs and those skilled in the art will understand that the invention described herein, even as applied to a CCD, is not limited in application to a specific type of CCD. Therefore, it should not be inferred from the fact that the invention is described with reference to a back-side illuminated, n-channel three-phase device that the invention is limited in application to a CCD, or that the invention, even as applied to a CCD, is limited to this specific type of CCD.
A charge-coupled device (CCD) may be made by processing a silicon die of p conductivity using conventional MOS technology to form a buried channel of n conductivity in an active region beneath the front or circuit side of the die (the side through which the die is processed). The channel is resolved into a linear array of like elementary zones by a clocking electrode structure which is composed of gate electrodes and overlies the circuit side of the die, and by application of selected potentials to the gate electrodes, a charge packet present in a given elementary zone of the channel may be advanced through the linear array of elementary zones, in the manner of a shift register, and discharged from the channel. In a multi-phase CCD, the gate electrodes are organized as multiple sets and different phases of a multi-phase clock signal are applied to the respective sets of gate electrodes.
Charge may be generated in the channel photoelectrically. Thus, if electromagnetic radiation enters the buried channel, it may cause generation of conduction electrons, and these conduction electrons may be confined in one of the elementary zones to form a charge packet.
A CCD may be used to generate an electrical signal representative of the distribution of light intensity over the active region of the CCD. In such an imaging CCD, there may be multiple imaging channels extending parallel to one another and each connected at one end to a common readout channel which extends perpendicular to the imaging channels. Charge packets are generated in the elementary zones or pixels of the imaging channels during an integration interval. Subsequently, during a readout interval, the charge packets are transferred from the imaging channels into the readout channel and the charge packets are transferred serially through the readout channel and deposited in an N+ floating diffusion. The size of a charge packet is measured by using a charge-sensing amplifier to sense the potential of the floating diffusion and the floating diffusion is then reset by a reset FET, with respect to which the floating diffusion acts as source and a reset diffusion acts as drain.
Referring to
FIG. 1
, the floating diffusion
2
is connected to the charge-sensing amplifier, which is typically implemented by a MOSFET
4
operating in the source follower configuration and developing an output signal across a load resistor
6
. The reset FET
16
has a gate RG for selectively connecting the floating diffusion
2
to the reset diffusion
18
.
In general, it is desirable that the source follower MOSFET
4
should generate a low noise output signal. To maintain a low noise output, the conversion gain of the floating diffusion needs to be high. This is achieved by minimizing the capacitance of the floating diffusion and all its associated parasitics. Since the gate capacitance of the MOSFET contributes directly to the total parasitic capacitance, in order to generate a low noise output signal, the source follower MOSFET should be small. On the other hand, the bandwidth of the source follower is limited by the capacitance that the MOSFET can drive. In a typical implementation of the arrangement shown in
FIG. 1
, the load resistor
6
is off-chip and therefore there can be a rather large parasitic capacitance associated with the load resistor. Accordingly, although the output structure shown in
FIG. 1
operates well for devices designed to function at a relatively low rate (less than 500 k pixels/sec.), it is not optimal for higher speed applications.
In order to operate at higher data rates, it is necessary to provide an output amplifier with a higher bandwidth. This can be accomplished by constructing a multistage source follower amplifier
8
, as shown in FIG.
2
. In order to maintain noise performance and high gain, it is important that the first stage MOSFET
10
be made small. Consequently, in order to operate at a high data rate, it is usual to employ a multistage source follower amplifier with the first stage being small and successive stages increasingly larger. For example, in one CCD that has been manufactured employing a two-stage amplifier, the first stage MOSFET
10
has l/w (length/width)=3/17 and the second stage MOSFET
12
has l/w=3/200.
Each source follower MOSFET in the multistage source follower amplifier requires its own load resistor. The load resistor
14
of the final MOSFET
12
may be off-chip and the loads for the first stage and any intermediate stages are typically provided by large MOSFETs (l/w=20/20) acting as constant current sources. This is a desirable configuration with respect to gain.
The current source MOSFETs serving as load transistors are fabricated on-chip, reducing the parasitic capacitance presented to the first stage and achieving a high bandwidth. Such loads are satisfactory for many applications where noise is not a severe limitation, but for low noise applications, such on-chip current sources are not acceptable because they are not only noisy but also tend to glow. The impact of glowing can be mitigated by placing the load transistor off-chip, but this will increase the parasitic capacitance and therefore reduce the bandwidth of the circuit. With proper design, it is possible to reduce the noise generated by the current source, but at the cost of speed.
An alternative to using load transistors as loads for the source follower MOSFETs is to employ on-chip resistors. For example, polysilicon resistors have been used in CMOS circuits. However, thin film resistors have better noise characteristics than polysilicon resistors.
A known method of fabricating a multiphase imaging CCD will now be described with reference to
FIGS. 3-7
.
FIG. 3
shows a silicon single crystal die
22
that has been processed in conventional fashion to form an active region
24
which extends partly into the die from the front side
26
thereof. The active region contains the imaging channels and the readout channel, but the channels are not shown in FIG.
3
. The active region
24
is surrounded by a thick layer of field oxide
28
. There are several apertures
30
(only two of which are shown in
FIG. 3
) in the field oxide near the periphery of the die. There is a thin layer of gate oxide (not shown in
FIG. 3
) over the die in the active region
24
and in the apertures
30
.
Referring to
FIG. 4
, the clocking electrode structure includes three sets of polysilicon conductor strips
32
1
,
32
2
and
32
3
, corresponding respectively to the three phases of the clock signal used to operate the CCD. The conductor strips
32
1
,
32
2
and
32
3
include respective gate electrodes
34
1
,
34
2
and
34
3
(
FIG. 6
) which extend over the thin oxide
36
, crossing the channels that are influenced by the gate electrodes. Each conductor strip includes a gate extension
38
(
FIG. 5
) which extends some distance over the field oxide. The conductor strips
32
of the three sets are formed sequentially, by depositing and patterning thr

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