Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-11-29
2001-10-02
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S003000, C438S255000, C438S398000
Reexamination Certificate
active
06297123
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a storage node, and more particularly, to a method of fabricating a storage node while simultaneously preventing neck-oxidation phenomena in the storage node.
2. Description of the Prior Art
A dynamic random access memory (DRAM) cell is composed of a pass transistor and a storage capacitor. The storage capacitor, disposed on the surface of a silicon oxide layer above a semiconductor wafer substrate, comprises a top electrode, a capacitor dielectric layer, and a storage node connected to a node contact. In the manufacturing processes for DRAM, an oxide-nitride-oxide (ONO) process is most commonly used to form the capacitor dielectric layer.
Please refer to FIG.
1
and FIG.
2
. FIG.
1
and
FIG. 2
are schematic diagrams of a prior art method of fabricating a storage node
20
of a DRAM cell. As shown in
FIG. 1
, a low-pressure chemical vapor deposition (LPCVD) process is performed to form a silicon oxide layer
14
on the surface of a substrate
12
of a semiconductor wafer
10
. A silicon oxide layer
14
, with a thickness of between six thousand and eight thousand angstroms (Å), is used to isolate the MOS transistor (not shown). Then, a lithographic process is performed on the surface of the silicon oxide layer
14
to define the pattern of a node contact
16
, and a node contact hole is formed in the silicon oxide layer
14
using an anisotropic dry etching process. An LPCVD process is performed on the surface of the semiconductor wafer
10
to form a conductive layer
18
of amorphous silicon (&agr;-Si). The conductive layer
18
covers the node contact hole to form a node contact
16
. The conductive layer
18
has a thickness between eight thousand and ten thousand angstroms to provide a sufficient surface area for storing charge.
As shown in
FIG. 2
, a lithographic process is performed on the surface of the conductive layer
18
to define the pattern of a storage node
20
. An anisotropic dry etching process is performed along the pattern to remove the excess regions of the conductive layer
18
down to the surface of the silicon oxide layer
14
, forming the storage node
20
. In the next step, an ultra high vacuum chemical vapor deposition (UHV-CVD) process is performed to uniformly form a polysilicon layer
22
with a hemispherical grain (HSG) structure on the surface of the storage node
20
. The HSG structure is used to increase the surface area for storing charge and reduce the charge refresh rate of the DRAM.
A capacitor dielectric layer (not shown) is formed on the surface of the polysilicon layer
22
. It is used to perform an ONO process to form a capacitor dielectric layer in a three-layer structure comprising a native oxide layer, a silicon nitride layer, and an oxygen-containing silicide layer. A native oxide layer (not shown), with a thickness of between ten and fifty angstroms, is first formed on the HSG structure surface of the polysilicon layer
22
. Then, a silicon nitride layer
24
, with a thickness of about fifty angstroms, is formed on the surfaces of the native oxide layer and the silicon oxide layer
14
. Finally, a high-temperature healing process is performed on the silicon nitride layer
24
in an oxygen-containing environment to repair the structure of the silicon nitride layer
24
and form an oxygen-containing silicide layer (not shown) on the surface of the silicon nitride layer
24
. The thickness of the oxygen-containing silicide layer is between forty and eighty angstroms.
The incubation times for the deposition of the silicon nitride layer
24
on the silicon oxide layer
14
and on the native oxide layer of storage node
20
are different. Hence, the silicon nitride layer
24
deposits to a thickness of nearly fifty angstroms on the surface of the storage node
20
, while the thickness of the silicon nitride layer
24
deposited on the silicon oxide layer
14
is only twenty to thirty angstroms. The thickness of the silicon nitride layer
24
on the silicon oxide layer
14
is sorely insufficient, which results in oxygen penetrating the silicon nitride layer
24
and entering the silicon oxide layer
14
. Oxygen diffuses through the polysilicon grain boundaries of the node contact
16
, and simultaneously oxidizes the grains and the grain boundaries of the polysilicon. This leads to neck-oxidation
26
occurring at the interface of the storage node
20
and the node contact
16
.
Consequently, the prior art method of fabricating the DRAM storage node
20
not only produces neck-oxidation and volume-expansion problems at the interface of the storage node
20
and the node contact
16
, but tilts the storage node
20
and cuts off the connection of the storage node
20
and the node contact
16
. The neck-oxidation situation is even more serious when the thickness of the capacitor dielectric layer is made thinner and thinner.
SUMMARY OF THE INVENTION
It is therefor an object of the present invention to provide a method of fabricating the storage node of a DRAM cell, while preventing neck-oxidation phenomena.
In a preferred embodiment, the present invention provides a method of fabricating the storage node on a semiconductor wafer, the semiconductor wafer comprising a substrate. The method forms a silicon oxide layer on the surface of the substrate, and then forms a node contact in the silicon oxide layer. A storage node formed on the silicon oxide layer connects to the node contact. During an ONO process of making a capacitor dielectric layer, an ion implantation process is performed as a surface process on the silicon oxide layer. A silicon nitride layer is then formed on the surfaces of the silicon oxide layer and the storage node. At last, a high-temperature oxidation process is performed.
It is an advantage of the present invention that the surface process is performed which reduces the difference in the incubation times for the deposition of a silicon nitride layer on the silicon oxide layer and for the deposition on the surface of the storage node. The problem of nonuniformity in the thickness of the silicon nitride layer is hence improved, and neck-oxidation is prevented at the interface of the storage node and the node contact.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5918123 (1999-06-01), Yang
patent: 6046059 (2000-04-01), Shen et al.
patent: 6218258 (2001-04-01), Joo
Sze Jhy-Jyi
Wang Chuan-Fu
Hsu Winston
Nguyen Tuan H.
United Microelectronics Corp.
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