Method of preventing high Icc at start-up in zero-power...

Details Method of preventing high Icc at start-up in zero-power... Method of preventing high Icc at start-up in zero-power...

2005-01-18

2005-01-18

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010

Reexamination Certificate

active

06845044

ABSTRACT:
A CMOS memory cell (FIG.1) is provided which includes a PMOS transistor (102) and an NMOS transistor (104) with a common floating gate and common drains configured to prevent a large drain of Icc current from a power supply during power-up. To prevent the large Icc during power-up, the threshold voltages of the PMOS transistor (102) and NMOS transistor (104) are set so that the PMOS transistor (102) and NMOS transistor (104) do not turn on together, irrespective of charge initially stored on the floating gate. Without such thresholds, a significant drain of current Icc from the power supply connection Vcc can occur since charge initially on the floating gate leaves both the PMOS transistor (102) and the NMOS transistor (104) on creating a path for Icc from Vcc to Vss.

REFERENCES:
patent: 4885719 (1989-12-01), Brahmbhatt
patent: 5128863 (1992-07-01), Nakamura et al.
patent: 5272268 (1993-12-01), Turner et al.
patent: 5272368 (1993-12-01), Turner et al.
patent: 5469076 (1995-11-01), Badyal et al.

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