Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-01-19
2002-06-04
Goudreau, George (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S687000, C438S652000, C438S653000, C438S697000, C438S704000, C438S720000, C438S725000, C438S749000
Reexamination Certificate
active
06399503
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a method of preventing the dishing phenomenon occurring atop a dual damascene structure of a semiconductor that causes the premature breakdown of a capacitor device.
2. Description of the Prior Art
A dual damascene process is the method of forming a conductive wire coupled with a plug. The dual damascene structure is used to connect devices and wires in a semiconductor wafer and insulated from other devices by surrounding inter-layer dielectrics (ILD).
Following the completion of the dual damascene process, a chemical mechanical polishing (CMP) process is always performed to planarize the surface of the semiconductor wafer and allow for subsequent deposition and photolithographic processes to be properly performed on the wafer and form good multilevel interconnects. As a result, the dual damascene structure is widely applied in the manufacturing process of integrated circuits. Thus, advancement in integrated circuit technology makes the improving of the yield of the dual damascene structure an important issue in the manufacturing process of integrated circuits.
Please refer to
FIG. 1
to
FIG. 4
of cross-sectional views of manufacturing a MOS capacitor
28
according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
has a substrate
12
, a first dielectric layer
14
composed of silicon dioxide positioned on the surface of the substrate
12
, and a dual damascene hole
16
. The dual damascene hole
16
consists of both a plug hole and a wire recess, stacked on the plug hole, positioned in the first dielectric layer
14
through to the surface of the substrate
12
.
As shown in
FIG. 2
, the method of manufacturing the MOS capacitor
28
according to the prior art first involves the formation of a barrier layer
18
covering the surface of the first dielectric layer
14
and the surfaces of both the walls and bottom of the dual damascene hole
16
, on the surface of the semiconductor wafer
10
. A physical vapor deposition (PVD) process is then performed to form a seed layer (not shown) on the surface of the barrier layer
18
, composed of tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), titanium (Ti), or metal materials with high melting points. By performing an electrical copper plating (ECP) process, a copper layer
20
is filled into the dual damascene hole
16
to form a dual damascene structure
22
on the surface of the seed layer covering the barrier layer
18
.
As shown in
FIG. 3
, a first CMP process is performed to remove portions of the copper layer
20
down to the surface of the first dielectric layer
14
. The surface of the copper layer
20
atop the dual damascene structure
22
is thus approximately aligned with that of the first dielectric layer
14
. As shown in
FIG. 4
, a second dielectric layer
24
made of an oxide-nitride-oxide (ONO) material, silicon nitride or materials with high effective dielectric constants, is formed on the surface of the semiconductor wafer
10
. A metal layer
26
is then formed in a predetermined area on the second dielectric layer
24
to complete the manufacturing of the MOS capacitor
28
comprised of the copper layer
20
, the second dielectric layer
24
and the metal layer
26
.
However, in the method of manufacturing the MOS capacitor
28
according to the prior art, the removal rate of the copper metal layer
20
is greater than that of the barrier layer
18
. As a result, the surface the copper metal layer
20
atop the dual damascene structure
22
is slightly lower than that of the first dielectric layer
14
to result in the dishing phenomenon. As well, the protrusion caused by the remaining barrier layer
18
at the interface of the first dielectric layer
14
and the copper layer
20
creates both the tip effect and a defect in the second dielectric layer
24
to induce premature breakdown of the MOS capacitor.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a method of preventing the dishing phenomenon on a semiconductor wafer, more specifically, to provide a method of preventing the dishing phenomenon occurring on a dual damascene structure of a semiconductor wafer.
In the preferred embodiment of the present invention, a semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and the surfaces of both the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method of the present invention first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure and portions of the barrier layer uncovered by the photoresist layer are then removed. A second CMP process is performed to remove portions of the copper layer so as to align the top of the copper layer in the dual damascene structure with the surface of the first dielectric layer following the stripping of the photoresist layer. A second dielectric layer, made of an oxide-nitride-oxide (ONO) material, silicon nitride or materials with high effective dielectric constants, is then formed on the surface of the semiconductor wafer. Finally, a metal layer is formed in a predetermined area on the second dielectric layer to complete the manufacturing of the MOS capacitor comprising of the copper layer, the second dielectric layer and the metal layer
It is an advantage of the present invention over the prior art that the dishing phenomenon caused by differences in the removal rate of both the copper layer and the barrier layer is prevented. As well, the present invention aligns the surface of the copper layer with that of the first dielectric layer atop the dual damascene structure so that protrusion, leading to the tip effect, at the interface of the first dielectric layer and the copper layer is also prevented. Therfore, the premature breakdown of the MOS capacitor as a result of the tip effect is prevented to increase both the efficiency and reliability of the MOS capacitor.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.
REFERENCES:
patent: 4833519 (1989-05-01), Kawtano
patent: 5776833 (1998-07-01), Chen et al.
patent: 6051496 (2000-04-01), Jang
patent: 6107193 (2000-08-01), Shiao et al.
patent: 6171963 (2001-01-01), Wang
Huang J. J.
Wu Kun-Lin
Goudreau George
Hsu Winston
United Microelectronics Corp.
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