Method of preprogramming before verifying in non-volatile memory

Details Method of preprogramming before verifying in non-volatile memory Method of preprogramming before verifying in non-volatile memory

1997-08-11

1998-07-21

Hoang, Huan

Static information storage and retrieval

Floating gate

Particular biasing

36518529, 36518533, 36518523, G11C 1606

Patent

active

057843180

ABSTRACT:
In a non-volatile semiconductor memory device, a memory cell array is composed of a plurality of memory cells. An address generating section sequentially generates an address from a head address to a last address for the memory cell array. A writing section performs a preprogramming operation to the memory cells of the memory cell array corresponding to the generated address. A verifying section performs a verifying operation to the memory cells of the cell array corresponding to the generated address. A detecting section detects a preprogramming operation period and a verifying operation period. A control section controls the writing section to be activated and the verifying section to be inactivated, during the preprogramming operation period, and controls the writing section to be inactivated and the verifying section to be activated, during the verifying operation period.

REFERENCES:
patent: 5361227 (1994-11-01), Tanaka et al.
patent: 5379256 (1995-01-01), Tanaka et al.
patent: 5590074 (1996-12-01), Akaogi et al.

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