Method of preparing antimony doped semiconductor with intrinsic

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437 12, H01L 21322

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055873251

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BRIEF SUMMARY
BACKGROUND OF THE INVENTION

This invention relates to a method of preparing semiconductor wafers with good intrinsic gettering capability for use in CMOS devices, especially highly antimony-doped epitaxial wafers.
Metallic contaminants in semiconductor substrates kill minority carriers, causing latch-up in bulk wafers and adversely affecting oxide and diode integrity in epitaxial wafers. It is therefore important to remove such contaminants from the substrate. This can be achieved by a process known as intrinsic gettering, which involves deliberately creating defects in the crystal lattice by incorporating oxygen atoms in the crystal. The oxygen atoms combine with the silicon in the lattice to form SiO.sub.2 nuclei. These create the crystal defects, which act as traps for the metallic contaminants.
In practice, it has been found difficult to get oxygen to precipitate in antimony-doped wafers because the antimony retards the oxygen precipitation.
Intrinsic gettering in substrates highly doped with antimony, which are used for epitaxial wafers, is of major importance, especially for ensuring gate oxide and diode integrity. Efforts have been made to achieve good gettering in N/N.sup.+ antimony doped epitaxial wafers [See, for example, J. O. Borland, and T. deacon, (Solid State Technology, Aug. 123 (1984)], but such efforts have generally been hampered by the oxygen retardation [See, T. Nozaki and Y. Itoh, J. Appl. Phys., 59, 2562 (1986 )]. while some mathematical models explain the oxygen retardation effect on the basis of electrical effects within the crystal, more recently it has been observed that crystal doped with tin, which has a similar ion size to antimony, does not exhibit this oxygen retardation behaviour. This suggests that the retardation is not caused solely by the large size of the antimony ions, as had previously been thought.
One method for achieving significant oxygen precipitation generally in silicon wafers is to grow oxygen nuclei or clusters at low temperatures (500.degree.-800.degree. C.) prior to processing at higher temperatures where oxygen precipitation occurs. At low temperatures, nucleation is easier because of the lower thermal energy available to break up the SiO.sub.2 nuclei as they form. At higher temperatures, oxygen diffusion increases and, for nuclei above a critical size, which depends on the temperature, growth occurs faster. Nuclei below the critical size tends to shrink due to the increased thermal energy to break up the bonds. Typical nucleation cycles are carried at a constant temperature (650.degree.-750.degree. C.) for fairly long time (8-48 h.). This method is not proved very effective for antimony doped wafers, and the long heat treatment induces warping in the wafer, which is highly detrimental to LSI processes.
Long treatment times at the low temperature (650.degree. C.) are required to produce enough nuclei above the critical size for growth during subsequent high temperature annealing. Kishino [S. Kishino et al., J. of Appl. Phys., 23, L9, 1984]showed that for lightly doped wafers the low temperature treatment time can be reduced by employing a nucleation growth (NG) cycle, wherein a treatment is first carried out at 650.degree. C. for about 2 hrs. followed by a treatment wherein the temperature is ramped up to about 900.degree. C. over a period of 1 to 2 hrs. By ensuring that the rate of increase of the critical site was lower than the growth rate of the nuclei, Kishino was able to obtain high defect densities without long cycle times.
Kishino carried out the NG cycle after an initial denuding treatment at 1200.degree. C. for 3 hrs. He did not address the problem of oxygen retardation that occurs in highly doped antimony wafers.


SUMMARY OF THE INVENTION

An object of the invention is to provide a method of preparing semiconductor wafers with improved gettering properties, especially wafers highly antimony-doped epitaxial wafers.
In accordance with the present invention a high temperature treatment is first carried out in on a semiconductor wafer for between

REFERENCES:
patent: 4548654 (1985-10-01), Tobin
patent: 4597804 (1986-07-01), Imaoka
patent: 4622082 (1986-11-01), Dyson et al.
patent: 4661166 (1987-04-01), Hirao
patent: 4851358 (1989-07-01), Huber
patent: 5141887 (1992-08-01), Liaw et al.
patent: 5286658 (1994-02-01), Shirakawa et al.

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