Method of predicting quiescent current variation of an...

Details Method of predicting quiescent current variation of an... Method of predicting quiescent current variation of an...

2006-06-27

2006-06-27

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system

Statistical measurement

C702S182000, C702S183000, C702S186000

Reexamination Certificate

active

07069178

ABSTRACT:
In exemplary embodiments, a method and computer program product for predicting quiescent current variation of an integrated circuit die include steps of: (a) receiving as input a value of a derating factor from a process monitor cell on an integrated circuit die and an on-chip variation of the derating factor; (b) constructing a curve fitting formula for estimating a quiescent current of the integrated circuit die as a function of the derating factor; (c) calculating minimum and maximum values of the quiescent current from the curve fitting formula, the value of the derating factor from the process monitor cell, and the on-chip variation of the derating factor to generate an estimate of minimum and maximum values for the quiescent current; and (d) generating as output the estimated minimum and maximum values of the quiescent current.

REFERENCES:
patent: 5944847 (1999-08-01), Sanada
Johnson et al., Models and Algorithms for Bounds on Leakage in CMOS Circuits, Jun. 1999, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18 No. 6, pp. 714-725.
Rajsuman R., lddq Testing for CMOS VLSI, Apr. 2000, Proceedings of the IEEE, vol. 88 No. 4, pp. 544-566.
Sabade et al., Neighbor Current Ratio (NCR): A New Metric for lddq Data Analysis, 2002, IEEE Computer Society, 9 pages.
Mao et al., Quiescent Current Testing Methodology for Detecting Leakage Faults, 90, IEEE, pp. 280-283.

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