Method of predicting lifetime of semiconductor integrated...

Details Method of predicting lifetime of semiconductor integrated... Method of predicting lifetime of semiconductor integrated...

2001-02-01

2003-10-14

Karlsen, Ernest (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06633177

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for measuring the lifetime of a semiconductor integrated circuit, including MOS devices like MOS transistors, and also relates to a method for reliability testing of the circuit.
BACKGROUND ART
A semiconductor integrated circuit is made up of various types of circuit elements. Among other things, the lifetime of an MOS transistor, one of those types of circuit elements, has an important effect on the reliability of the circuit.
In recent years, as the number of devices integrated in a single semiconductor integrated circuit has been increased, a gate insulating film for an MOS transistor has been thinned considerably. Thus, the degradation of the gate insulating film determines the lifetime of the MOS transistor and eventually has a considerable effect on the lifetime of the circuit itself.
In evaluating the reliability of a semiconductor integrated circuit according to a known technique, an MOS capacitor under test, including a gate insulating film with a relatively wide area, is made in place of multiple small-sized MOS transistors included in the circuit. And the lifetime of the gate insulating film of the capacitor is predicted. That is to say, in the prior art, the reliability of a semiconductor integrated circuit has been evaluated on the supposition that the MOS capacitor including the gate insulating film with a relatively wide area is equivalent to the great number of small-sized MOS transistors.
For example, the lifetime of a semiconductor integrated circuit, made up of one hundred MOS transistors each having an area of 1 &mgr;m
2
, has been regarded as equivalent to the lifetime of one MOS capacitor having an area of 100 &mgr;m
2
. In other words, the lifetime of the circuit, made up of one hundred MOS transistors each having the area of 1 &mgr;m
2
, has been believed a time it takes for a first one of the one hundred MOS transistors to cause a dielectric breakdown (i.e., the amount of leakage current flowing there exceeds its critical value). And the time has been believed equal to the lifetime of the MOS capacitor with the area of 100 &mgr;m
2
, or a time it takes for the MOS capacitor to cause a dielectric breakdown.
Specifically, in an MOS transistor including a gate insulating film with a thickness of more than about 4 nm, a steep rise in leakage current, resulting from a stress placed on the transistor, i.e., the generation of hard breakdown (HBD), is identifiable. A gate insulating film with that thickness will be herein called a “thick gate insulating film”. In this case, a time it takes for one of multiple MOS transistors in a semiconductor integrated circuit to cause the HBD may be estimated by using an MOS capacitor under test. And the estimated time may be regarded as the circuit's lifetime.
However, as for an MOS transistor including a gate insulating film with a thickness of about 4 nm or less, i.e., a gate insulating film in which a direct tunneling current is prevailing, it is hard to identify the generation of the HBD. A gate insulating film with that thickness will be herein called a “thin gate insulating film”.
That is to say, the thinner the gate insulating film of an MOS transistor, the less and less often the obvious dielectric breakdown is observable. Thus, the lifetime of a semiconductor integrated circuit cannot be predicted accurately enough.
DISCLOSURE OF INVENTION
In view of these respects, an object of the present invention is to predict the lifetime of a semiconductor integrated circuit accurately enough even when a thin gate insulating film is used for an MOS device.
To achieve this object, the present inventor carried out various types of researches on the lifetime of a semiconductor integrated circuit. As a result, I made the following findings.
If a stress is continuously placed on an MOS transistor including a gate insulating film with a thickness of about 6 nm or less, the generation of a soft breakdown (SBD) is identifiable. According to the accepted standards, the SBD refers to a state where the dielectric breakdown has not occurred yet. However, a very small amount of leakage current flows through a gate insulating film in the SBD state. Specifically, the SBD herein means a phenomenon that the density of leakage current, flowing locally through a particular region of the gate insulating film, has increased 100 times or more compared to the density before the stress is placed and is now greater than the density of leakage current flowing through any other region. As for an MOS transistor including a gate insulating film with a thickness of more than about 6 nm, it is difficult to identify the generation of the SBD separately from the HBD. This is because when the conditions of SBD generation are met by the transistor, the HBD and SBD much more likely occur at a time in that transistor.
Hereinafter, the SBD will be described with reference to FIG.
1
.
FIG. 1
is a graph illustrating variations of gate current-gate voltage (I
G
−V
G
) characteristics obtained by repeatedly applying a constant voltage stress to an MOS capacitor including a gate insulating film with a thickness of 2.4 nm and an area of 0.01 mm
2
.
As shown in
FIG. 1
, once the stress voltage is applied, the I
G
−V
G
characteristic changes from its initial state initial where the direct tunneling current is prevailing into a B-SILC state. In the B-SILC state, a B-mode stress induced leakage current, resulting from the generation of the SBD, flows through a local region of the gate insulating film. The B-mode stress induced leakage current will be herein called a “B-SILC current”.
Also, as the stressing time passes, the B-SILC current increases. Accordingly, the I
G
−V
G
characteristic in the B-SILC state sequentially changes from the curve a into the curve d by way of the curves b and c.
E. Wu et al. reported in IEDM (1998) 187 that where the SBD has occurred in a region of an MOS transistor where the gate electrode overlaps with the source or drain region, the MOS transistor cannot operate anymore. That is to say, E. Wu et al. also regards a time it takes for one of multiple MOS transistors in a semiconductor integrated circuit to cause the SBD as the circuit's lifetime. This approach will be herein called a “first lifetime prediction approach”.
Following is the conclusion of my analysis on the “first lifetime prediction approach”.
FIG. 2
illustrates relationships between the leakage current I
G
and stressing time where a constant voltage stress (CVS) of −4.3 V was applied to two MOS capacitors (which will be herein called “samples A and B”) formed on the same semiconductor substrate. It should be noted that “−” herein means that the gate electrode is at the lower potential level. Also, the samples A and B had gate insulating films with the same configuration (i.e., thickness: 2.4 nm; area: 0.01 mm
2
) and the stress was placed differently on the samples A and B. More specifically, even after the SBD generation had been identified, the stress was continuously imposed on the sample A. As for the sample B on the other hand, the instant the SBD generation was identified, the stressing was once suspended and then the stressing was started again. In
FIG. 2
, the graph plotted for sample B(
1
) illustrates a relationship between the leakage current and stressing time before the stressing was suspended. On the other hand, the graph plotted for sample B(
2
) illustrates a relationship between the leakage current and stressing time after the stressing was restarted.
As shown in
FIG. 2
, when the SBD occurs, the leakage current I
G
of the sample A rises steeply and then increases relatively gently. In contrast, after the stressing is restarted, the leakage current I
G
of the sample B (see the graph for the sample B(
2
)) increases gradually but is smaller than the leakage current I
G
of the sample A.
That is to say, the level of the leakage current I
G
flowing after the SBD generation changes greatly depending on whether or not the stress is continuously placed after

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