Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Power system
Reexamination Certificate
2005-03-15
2005-03-15
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Power system
C703S022000, C716S030000, C716S030000
Reexamination Certificate
active
06868374
ABSTRACT:
A method and system for testing the compliance of a distribution of I/O circuits in a semiconductor chip with voltage (IR) and electromigration (EM) limits. Maximum and average currents for the I/O circuits are calculated. A resistance model for the power distribution network of the chip is created, and the I/O circuit currents are indexed to corresponding nodes in the resistance model. Average current demand of the logic circuitry of the chip is also calculated and indexed to nodes in the resistance model. The resistance model with indexed currents is then solved to determine voltages at the nodes. The voltages are checked for compliance with IR and EM limits, and a report is produced. If violations of the IR and EM limits are detected, the placement of the I/O circuits in the power distribution network may be revised to bring the design into compliance with IR and EM requirements.
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Ditlow Gary S.
Proctor Robert A.
Broda Samuel
Connolly Bove & Lodge & Hutz LLP
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