Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-02-14
2002-11-26
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010, C324S071100
Reexamination Certificate
active
06486692
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for positive mobile iron contamination (PMIC) detection.
DESCRIPTION OF THE PRIOR ART
One of the most serious problems encountered during early MOS technology development was an electrical instability now known as “the mobile ion problem”. MOS transistor devices fabricated by using planar technology exhibit threshold voltages (VT) more negative than predicted by theoretical calculation. In addition, under a bias at elevated temperature, MOS transistor devices are extremely unstable. As the positive gate bias increases, the threshold voltages (VT) of MOS transistor devices will shift to more negative values. The magnitude and rate of the VT shift increases with temperature. On the other hand, a negative gate bias, without the shift effect of VT, produces stable device characteristics. It is now well-established that the instability in early planar processed MOS transistors was due to the drift of positive mobile irons(particularly Na+ and K+) in the gate oxide.
However, positive mobile ions are often introduced into the gate oxide during “metals and planarization etching” and “photoresist stripping”, and these manufacturing processes are indispensable steps to multilayer metal processing (MLM processing). Therefore, as the dimensions of devices shrink, it takes a wafer level reliability(WLR) test to determine which manufacturing process has introduced PMIC, and further to seek the solution to reduce or eliminate PMIC.
Usually, the common strategies for reducing PMIC include reducing the PMIC concentration in the gate oxide, rendering the irons in the gate oxide immobile, neutralizing the irons in the gate oxide. For example, by depositing phosphorus silicon glass (PSG) over the surface of the gate oxide, implanting phosphorus ions in the polysilicon gate, and using PSG as interface dielectrics, the gettering of the positive mobile ions to the gate oxide is obtained. Or, by doping chlorine ions into Si/SiO
2
interface during the gate oxide growth, and using chlorine ions during pre-oxidation cleaning of furnace tubes, the positive mobile ions in the gate oxide are neutralized. Or, by improving the impurities of the chemicals or gases, and improving the equipment and wafer cleaning technique, a cleaner fabrication line is provided.
For the present technique, the wafer level reliability (WLR) test usually measures the quantity and location of PMIC along with the apparatuses of SEM/EDS, XSEM, XTEM, and three-dimensional SIMS etc. These apparatuses may precisely detect the quantity and location of PMIC, but there are several drawbacks. First, these apparatuses are very expensive and need experts to operate and analyze the results. Secondly, all these apparatuses use destructive measuring methods, so the throughput is very low. It is therefore considered desirable to explore how to complete the WLR test under the conditions of non-destructivity, low cost, and high throughput.
During the fabricating process of integrated circuits, the concentration of PMIC is usually calculated by using the difference value of the flatband voltage when applying bias and temperature stress to an MOS capacitance to get a Capacitance-Voltage (C-V) curve.
FIGS.
1
A~
1
D are schematic diagrams showing how PMIC is measured by using the bias and temperature stress(BTS) technique. Before any bias and temperature stress are applied, the positive mobile ions are evenly distributed in the gate oxide, as shown in FIG.
1
A. First, a positive bias of magnitude about 1~2 MV/cm is applied to the polysilicon or metal gate in order to push the mobile positive ions in the gate oxide to the interface between the semiconductor substrate and the gate oxide, as shown in FIG.
1
B. Then, the stress temperature is gradually raised to 100 ~200° C., and this temperature is maintained for 3~50 minutes. Then, the stress temperature is gradually decreasing to room temperature, and the positive bias is removed to measure an electric field change. Then, a negative bias of the magnitude about −1~−2 MV/cm is applied to the polysilicon/ metal gate, and all the positive mobile ions in the gate oxide are attracted to the interface between the polysilicon/metal gate and the gate oxide, as shown in
FIG. 1C
, and all the steps mentioned above are repeated to measure another electric field change. Thus, the concentration of PMIC can be calculated through the difference value of the flatband voltage, as shown in
FIG. 1D
; that is:
N
M
=
C
OX
1
Δ
V
FB
1
q
However, this technique is applicable to thin oxide layers, but unable to monitor PMOS in thick oxide layers.
FIGS.
2
A~
2
C are schematic diagrams showing that the triangular voltage scan(TVS) technique is used to measure PMIC. As shown in FIGS.
2
A~
2
B, the TVS technique first applies a positive bias VG and a stress temperature T to the polysilicon/metal gate. Then, the stress temperature T is lowered drastically to a low temperature of about −20° C. to trap the positive mobile ions into the interface between the semiconductor substrate and the gate oxide. At this stage, the positive mobile ions don't have enough kinetic energy, so there is no current generated even though the electric field changes. Then, the stress temperature T is gradually rising from the low temperature at the rate of about 0.5°C./sec. When the stress temperature T rises, the positive mobile ions trapped into the interface between the semiconductor substrate and the gate oxide will be thermally excited out. In
FIG. 2C
, two peaks of the displacement current are the locations where Na
+
and K
+
are thermally excited out, respectively. Since the excited energy of Na
+
is smaller than that of K
+
; that is E(Na
+
)<E(K
+
), the displacement current peak of K
+
will be on the right side of that of Na
+
. Further, the quantities of Na
+
and K
+
are respectively proportional to the areas under the current peaks of Na
+
and K
+
.
However, a displacement current detected by using this technique is very weak, so it takes a larger chip area and the junction capacitance also causes a very large experimental error.
FIGS.
3
A~
3
C are schematic diagrams of MPIC also measured by using the TVS technique. As shown in FIGS.
3
A~
3
B, the TVS technique first applies the positive bias (VG) and the stress temperature T to the polysilicon/metal gate, so as to keep the PMIC in the interface between the semiconductor substrate and the gate oxide by using the electric field. Then, the positive bias (VG) is adjusted to the initial condition and then gradually decreased at the rate of 5~100 mV/s. When the electric field changes, the mobile positive ions will drift and diffuse into the interface between the polysilicon/metal gate and the gate oxide. In
FIG. 3C
, the two current peaks are the locations where Na
+
and K
+
are resolved respectively, and the quantities of Na
+
and K
+
are respectively proportional to the areas under the current peaks of Na
+
and K
+
, as shown in FIG.
2
C.
However, this technique is only applicable to thin oxide layers, and cannot be used to monitor PMIC in thick oxide layers.
SUMMARY OF THE INVENTION
Therefore, it is the principal object of the invention to provide an apparatus and method for measuring PMIC, wherein the location and quantity of PMIC can be rapidly measured during the WLR test.
It is another object of the invention to provide an apparatus and method for measuring PMIC, wherein the kinetic energies of Na
+
and K
+
are raised by using the power dissipation produced by polysilicon resistance, so as to effect the measurement within a short time.
It is another object of the invention to provide an apparatus and method for measuring PMIC, wherein the measurement of PMIC can be completed nondestructively with the advantages of low cost and high resolution.
To achieve the objects mentioned above and others, the invention provides an apparat
Ladas & Parry
Nguyen Vinh P.
Patel Paresh
Winbond Electronics Corp.
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