Radiant energy – Photocells; circuits and apparatus – With circuit for evaluating a web – strand – strip – or sheet
Reexamination Certificate
1999-12-16
2002-08-13
Krizek, Janice L. (Department: 3652)
Radiant energy
Photocells; circuits and apparatus
With circuit for evaluating a web, strand, strip, or sheet
C356S401000
Reexamination Certificate
active
06433352
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. Hei 10(1998)-358772 filed on Dec. 17, 1998, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of positioning a semiconductor wafer, and particularly to a method of positioning each of a plurality of shot areas to an exposure position in turn by a step and repeat system, when the plurality of shot areas are regularly arranged on the wafer and a circuit pattern is exposed in each shot area.
2. Description of the Related Art
Semiconductor devices such as ICs or LSIs have been made more and more minute and dense. When exposing a circuit pattern formed on a photomask or a reticle in multiple shot areas on a semiconductor wafer one by one with an exposure equipment, it is desired to position each shot area to an exposure position of the exposure equipment with high accuracy.
For the exposure equipment, a step and repeat system is often used, in which a semiconductor wafer fixed on a wafer stage is positioned to an exposure position for each shot area to be exposed through a circuit pattern. With the exposure equipment using the step and repeat system, each shot area is positioned to the exposure position while a semiconductor wafer is positioned on the wafer stage, as disclosed in Japanese Unexamined Patent Publication No. Hei 6(1994)-224103, for example. The semiconductor wafer is positioned with respect to the wafer stage based on alignment marks provided on each semiconductor wafer.
As shown in FIG.
10
A and
FIG. 10B
, shot areas
11
on a semiconductor wafer are usually lined up crosswise at even intervals. Accordingly, with the exposure equipment using the step and repeat system, the wafer stage on which the semiconductor wafer is fixed is moved in order with a specified step pitch to position each shot area
11
to the exposure position in turn. However, when the semiconductor wafer itself is warped as shown in FIG.
11
A and
FIG. 10B
, each of the actual step pitches becomes smaller than the specified step pitch, even more so for a position closer to the rim of the semiconductor wafer.
In addition, the position of an alignment mark to be detected on the warped semiconductor wafer is radially or circumferencially displaced with respect to the position of an alignment mark on an unwarped wafer, which causes inaccurate positioning of the shot center in each shot area
11
.
Conventionally, to solve this problem, each shot area
11
is positioned and adjusted precisely to the exposure position every time each shot area
11
is stepped to the exposure position. However, positioning and adjusting each shot area
11
precisely to the exposure position causes a problem of significantly reduced throughput.
SUMMARY OF THE INVENTION
The present invention solves the problems mentioned above. It is an object of the present invention to provide a method of positioning a semiconductor wafer that allows high-accuracy positioning of each shot area to the exposure position without reducing the throughput even if the semiconductor wafer is warped.
Accordingly, the present invention provides a method of positioning a semiconductor wafer by a step and repeat system comprising the steps of fixing a semiconductor wafer on a wafer stage, the semiconductor wafer including a plurality of shot areas regularly arranged thereon, and positioning each of the shot areas in turn to an exposure position by the step and repeat system, wherein a step pitch to move each of the shot areas to the exposure position is adjusted by a magnitude of warpage of the semiconductor wafer.
REFERENCES:
patent: 5502311 (1996-03-01), Imai et al.
patent: 5525808 (1996-06-01), Irie et al.
patent: 5710620 (1998-01-01), Taniguchi
patent: 5793473 (1998-08-01), Koyama et al.
patent: 6-224103 (1994-08-01), None
Krizek Janice L.
Nixon & Vanderhye P.C.
LandOfFree
Method of positioning semiconductor wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of positioning semiconductor wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of positioning semiconductor wafer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2881016