Method of planarizing wafers with shallow trench isolation

Details Method of planarizing wafers with shallow trench isolation Method of planarizing wafers with shallow trench isolation

1996-07-25

1999-02-16

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438430, 438692, 438699, H01L 2176

Patent

active

058720430

ABSTRACT:
This invention describes a method of using Chemical Mechanical Polishing to planarize integrated circuit wafers using shallow trench isolation to provide isolation between devices in the wafer. After the material used to fill the shallow trenches has been formed a layer of Spin On Glass is formed over the material used to fill the shallow trenches. The polishing rate for the material used to fill the shallow trenches is at least twice as large as the polishing rate of the Spin On Glass. This difference in polishing rate causes the Spin On Glass to be the controlling factor in the overall polishing rate and a planar surface free of dishing or unwanted residue is achieved. In at least one of the embodiments the rate of change of the polishing pad temperature can be used to determine the end point of the polishing.

REFERENCES:
patent: 5246884 (1993-09-01), Jaso et al.
patent: 5346584 (1994-09-01), Nasr et al.
patent: 5560802 (1996-10-01), Chisolm
"SOG Smoothing Technique For Planarization of Shallow Trench Isolation" by Lai-Juh Chen et al. 1996 Proceedings First International Chemical-Mechanical Polish (CMP) For VLSI/ULSI Multilevel Interconnection Conference (CMP-MIC), Feb. 22-23, 1996, pp. 307-314.

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