Method of planarizing interlayer dielectric

Details Method of planarizing interlayer dielectric Method of planarizing interlayer dielectric

1996-07-26

1998-05-05

Niebling, John

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

438974, 438691, 1566361, H01L 21469

Patent

active

057473854

ABSTRACT:
A method of planarizing an interlayer dielectric layer in a semiconductor integrated circuit device is provided, which method can remove remaining parts of the dielectric layer without removing the surface of the layer itself at a high throughput. After an insulating layer is formed on a chief surface of the semiconductor substructure, an interconnection layer having interconnection lines is formed on the insulating layer. An interlayer dielectric layer is formed on the insulating layer so as to cover the interconnection layer. The dielectric layer has steps or protrusions at positions corresponding to the underlying interconnection lines of the interconnection layer. Next, a patterned resist film is formed on the interlayer dielectric layer so as to have an inverted geometric shape relative to that of the interconnection layer. Then, using the patterned resist film as a mask, the interlayer dielectric layer is selectively etched to thereby partially remove the top of the protrusions by a predetermined depth. Subsequently, a beam of hard or solid particles is emitted so as to collide with the remaining parts of the protrusions of the interlayer dielectric layer, thereby removing the protrusions.

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Sivaram et al; "Planarizing Interlevel Dielectrics by Chemical-Mechanical Polishing"; May 1992; pp. 87-91; Solid State Technology.
Ali et al; "Chemical-mechanical polishing of interlayer dielectric: A review"; Oct. 1994; pp. 63-64, 66, 68; Solid State Technology.
Warnock; "A Two-Dimensional Process Model for Chemimechanical Polish Planarization"; Aug. 1991; pp. 2398-2402; J. Electrochem. Soc. vol. 138, No. 8.

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