Method of planarizing integrated circuits with fully recessed is

Details Method of planarizing integrated circuits with fully recessed is Method of planarizing integrated circuits with fully recessed is

1997-07-23

1999-12-28

Fourson, George R.

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438692, 438959, H01L 21762

Patent

active

060081074

ABSTRACT:
An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

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