Method of planarizing a semiconductor die

Details Method of planarizing a semiconductor die Method of planarizing a semiconductor die

2005-11-29

2005-11-29

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

Reexamination Certificate

active

06969687

ABSTRACT:
A method of CMP planarizing a silicon dioxide layer on a silicon nitride in the semiconductor die is disclosed. A wafer has a plurality substantially identical semiconductor dies defined on the wafer. Each of the dies is separated from one another by a scribe line. A layer of silicon nitride is formed on the planar surface of the wafer where the silicon nitride has a top surface which is substantially parallel to the planar surface. A layer of silicon dioxide is deposited on the top surface with the silicon dioxide varying in height above the top surface. A mask is formed across the wafer, including on the scribe line, where the mask has a plurality of locations with each location having a differing density of gap-to-pillar ratio, which is proportional to the height of the silicon dioxide above the top surface. The silicon dioxide is anisotropically etched through each gap of the mask across the entire wafer where each gap is etched by the same amount in the height direction. CMP is then used to planarize the silicon dioxide to the top surface of the silicon nitride across the entire wafer.

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“Using Smart Dummy Fill And Selective Reverse Etch Back for Pattern Density Equalization,” Brian Lee, et al, published in CMP-MIC Conference, pp. 1-9, Mar. 2000.
European Search Report corresponding to the related EP Patent Application No. 03256830.5 mailed on Aug. 4, 2005.

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