Method of planarizing a semiconductor die

Details Method of planarizing a semiconductor die Method of planarizing a semiconductor die

2003-04-25

2004-03-09

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C424S435000

Reexamination Certificate

active

06703318

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of planarizing a layer of a first material, and more particularly a dieletric layer, using chemical mechanical polishing techniques on a semiconductor die.
BACKGROUND OF THE INVENTION
Chemical mechanical polishing (CMP) is a well-known method to planarize a material used in semiconductor processing. Typically, the material to be planarized is a dieletric, such as silicon dioxide, which has been deposited on another dieletric such as silicon nitride. Further, the silicon nitride has a top planar surface with the silicon dioxide deposited thereon. However, because there are trenches in the substrate and with holes in the silicon nitride leading to the trenches, the silicon dioxide deposited on the silicon nitride will flow through the holes in the silicon nitride into the trenches in the substrate, thereby causing an uneven level above the top planar surface of the silicon nitride. Thus, the height of the silicon dioxide above the top planar surface of the silicon nitride can vary substantially. In the CMP method, it is desired to polish or remove the silicon dioxide so that it is planar with the top planar surface of the silicon nitride.
One prior art method to attempt to level the silicon dioxide is to create artificial dummy diffusion regions in the substrate of large field areas and filling it with oxide, but this does not address the large active areas and CMP's dishing effect associated with the large active areas. In other words, this method alone does not address the problem of the planarization of all the areas of the wafer. Another prior art solution is to mask certain portions of the silicon dioxide where the height of the silicon dioxide above the top planar surface of the silicon nitride is substantial. The silicon dioxide in the masked portion is removed thereby removing a substantial portion of the silicon dioxide in the portion where the height of the silicon dioxide above the top planar surface is substantial. This, however, creates a well-known undesired effect called “dishing” wherein polishing of the silicon dioxide causes the removal of silicon nitride in certain areas
Finally, in an article entitled “Using Smart Dummy Fill and Selective Reverse Etch Back for Pattern Density Equalization,” by Brian Lee, Duane S. Boning, Dale L. Hetherington, and David J. Stein, published in CMP-MIC conference dated March, 2000, the authors suggested a dummy mask with a certain lay out density patterns and then removing silicon dioxide from just those selected etch back cells wherein a certain percentage of the underlying silicon dioxide is removed and is inverse to that of the targeted film density. This technique, however, suffers from the disadvantage that it does not take into account silicon dioxide across the entire wafer of semiconductor substrate, including silicon dioxide between the scribe lines separating the dies.
SUMMARY OF THE INVENTION
Accordingly, in the present invention, a method of planarizing a first material on a second material of a semiconductor die is disclosed. A plurality of substantially identical semiconductor dies are defined on a semiconductor wafer with the wafer having a planar surface. The plurality of dies are separated from one another by a scribe line. A layer of the second material is formed on the planar surface of the semiconductor wafer, wherein the layer of the second material has a top surface which is substantially parallel to the planar surface. A layer of the first material is on the top surface and the layer of the first material varies in a height direction above the top surface. A mask is formed across the wafer, where the mask has a plurality of locations with each location having differing density of gap-to-pillar ratio, which is proportional to the height of the first material above the top surface. The first material is anisotropically etched through each gap of the mask across the entire wafer wherein each gap is etched by the same amount in the height direction. CMP is then used to planarize the first material to the top surface across the wafer.


REFERENCES:
patent: 5928960 (1999-07-01), Greco et al.
patent: 6498072 (2002-12-01), Azuma
patent: 6541324 (2003-04-01), Wang

Affiliated with

Also associated with

Rating

Method of planarizing a semiconductor die does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of planarizing a semiconductor die, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of planarizing a semiconductor die will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3278668